| 國立交通大學 |
2015-07-21T11:20:58Z |
A 40 nm 512 kb Cross-Point 8 T Pipeline SRAM With Binary Word-Line Boosting Control, Ripple Bit-Line and Adaptive Data-Aware Write-Assist
|
Lien, Nan-Chun; Chu, Li-Wei; Chen, Chien-Hen; Yang, Hao-I.; Tu, Ming-Hsien; Kan, Paul-Sen; Hu, Yong-Jyun; Chuang, Ching-Te; Jou, Shyh-Jye; Hwang, Wei |
| 國立交通大學 |
2015-07-21T08:31:00Z |
A 40nm 1.0Mb 6T Pipeline SRAM with Digital-Based Bit-Line Under-Drive, Three-Step-Up Word-Line, Adaptive Data-Aware Write-Assist with VCS Tracking and Adaptive Voltage Detector for Boosting Control
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Liao, Wei-Nan; Lien, Nan-Chun; Chang, Chi-Shin; Chu, Li-Wei; Yang, Hao-I; Chuang, Ching-Te; Jou, Shyh-Jye; Hwang, Wei; Tu, Ming-Hsien; Huang, Huan-Shun; Wang, Jian-Hao; Kan, Paul-Sen; Hu, Yong-Jyun |
| 國立交通大學 |
2015-07-21T08:30:59Z |
Method for Resolving Simultaneous Same-Row Access In Dual-Port 8T SRAM with Asynchronous Dual-Clock Operation
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Lien, Nan-Chun; Chuang, Ching-Te; Wu, Wen-Rang |
| 國立交通大學 |
2014-12-16T06:14:56Z |
SRAM based on 6 transistor structure including a first inverter, a second inverter, a first pass-gate transistor, and a second pass-gate transistor
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CHUANG Ching-Te; Jou Shyh-Jye; Hwang Wei; Lin Yi-Wei; Tsai Ming-Chien; Yang Hao-I; Tu Ming-Hsien; Shih Wei-Chiang; Lien Nan-Chun; Lee Kuen-Di |
| 國立交通大學 |
2014-12-16T06:14:56Z |
Oscillator based on a 6T SRAM for measuring the Bias Temperature Instability
|
Chuang Ching-Te; Jou Shyh-Jye; Hwang Wei; Tsai Ming-Chien; Lin Yi-Wei; Yang Hao-I; Tu Ming-Hsien; Shih Wei-Chiang; Lien Nan-Chun; Lee Kuen-Di |
| 國立交通大學 |
2014-12-16T06:14:50Z |
CONTROL CIRCUIT OF SRAM AND OPERATING METHOD THEREOF
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CHUANG Ching-Te; LIEN Nan-Chun; LIAO Wei-Nan; CHU Li-Wei; CHANG Chi-Shin; TU Ming-Hsien |
| 國立交通大學 |
2014-12-16T06:13:57Z |
Threshold voltage measurement device
|
Chuang Ching-Te; Jou Shyh-Jye; Lin Geng-Cing; Wang Shao-Cheng; Lin Yi-Wei; Tsai Ming-Chien; Shih Wei-Chiang; Lien Nan-Chun; Lee Kuen-Di; Chu Jyun-Kai |
| 國立交通大學 |
2014-12-16T06:13:49Z |
Oscillato based on a 6T SRAM for measuring the bias temperature instability
|
Chuang Ching-Te; Jou Shyh-Jye; Hwang Wei; Tsai Ming-Chien; Lin Yi-Wei; Yang Hao-I; Tu Ming-Hsien; Shih Wei-Chiang; Lien Nan-Chun; Lee Kuen-Di |
| 國立交通大學 |
2014-12-16T06:13:47Z |
Static random access memory apparatus and bit-line voltage controller thereof
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Chuang Ching-Te; Lien Nan-Chun; Liao Wei-Nan; Chang Chi-Hsin; Yang Hao-I; Hwang Wei; Tu Ming-Hsien |
| 國立交通大學 |
2014-12-12T02:42:47Z |
低操作電壓奈米級靜態隨機記憶體電路設計
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連南鈞; Lien, Nan-Chun; 吳文榕; 莊景德; Wu, Wen-Rong; Chuang, Ching-Te |
