臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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Institution	Date	Title	Author
南台科技大學	2000-03	AES 第一回合演算法的比較	王釋毅; 賴溪松; 葉義雄; 林祝興; 孫宏民; 王立洋; Lih-Yang Wang
南台科技大學	2000	On the hardware design for DES cipher in tamper resistant devicesagainst differential fault analysis	Lih-Yang Wang ; Chi-Sung Laih; Hang-Geng Tsai;Nern-Min Huang
南台科技大學	1995-01	Performance-Directed Compaction for VLSI Symbolic Layout	Lih-Yang Wang; Yen-Tai Lai; Bin-Da Liu; Ting-Chun Chang;王立洋
南台科技大學	1993-05	Layout compaction with minimized delay bound on timing critical paths	Lih-Yang Wang; Yen-Tai Lai; Bin-Da Liu; Tin-Chung Chang;王立洋; 劉濱達
南台科技大學	1993	Performance-Driven Global Routing Based on Simulated Evolution	Lih-Yang Wang; Bin-Da Liu; Yen-Tai Lai; Ming-Yuan Yeh; 王立洋;劉濱達
南台科技大學	1993	A graph-based simplex algorithm for minimizing the layout size andthe delay on timing critical paths	Lih-Yang Wang; Yen-Tai Lai; Bin-Da Liu; Ting-Chun Chang; 王立洋;劉濱達
南台科技大學	1992-07	Neural Nerwork on Two Dimensional IC Layout Compaction	Lih-Yang Wang; Kun-Nern Chen; Yen-Tai Lai; Bin-Da Liu;王立洋
南台科技大學	1991	Simultaneous Pin Assignment and Global Routing for Custom VLSI Design	Lih-Yang Wang; Yen-Tai Lai; Bin-Da Liu; 王立洋;劉濱達
南台科技大學	1991	Two-Dimensional Layout Compaction by Neural Optimization Network	Lih-Yang Wang; Yen-Tai Lai; Bin-Da Liu

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