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Taiwan Academic Institutional Repository >
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"lin chen shang"
Showing items 1-10 of 70 (7 Page(s) Totally)
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| 國立臺灣大學 |
1998-12 |
A Global Parallelization Scheduling Algorithm for Automated Synthesis of Digital Systems
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Chen, T.; 林呈祥; Chen, T.; Lin, Chen-Shang |
| 淡江大學 |
1995-11-01 |
Test set compaction for combinational circuits
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張昭憲; Chang, Jau-shien; Lin, Chen-shang |
| 國立臺灣大學 |
1995-11 |
Fast fault simulation for BIST applications
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Kung, Chen-Pin; Huang, Chun-Jieh; Lin, Chen-Shang |
| 國立臺灣大學 |
1995-09 |
OBDD variable ordering by interleaving compacted clusters
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Yeh, Fu-Min; Lin, Chen-Shang |
| 淡江大學 |
1995-01-01 |
Test time reduction for scan-designed circuits by sliding compatibility
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張昭憲; Chang, Jau-shien; Lin, Chen-shang |
| 淡江大學 |
1994-11-16 |
Test time reduction for scan-designed circuits by sliding compatibility
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張昭憲; Chang, Jau-shien; 林呈祥; Lin, Chen-shang |
| 國立臺灣大學 |
1994-11 |
Test time reduction for scan-designed circuits by sliding compatibility
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Chang, Jau-Shien; Lin, Chen-Shang |
| 淡江大學 |
1994-10-02 |
A test clock reduction method for scan-designed circuits
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張昭憲; Chang, Jau-shien; 林呈祥; Lin, Chen-shang |
| 國立臺灣大學 |
1994-10 |
A test clock reduction method for scan-designed circuits
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Chang, Jau-Shien; Lin, Chen-Shang |
| 國立臺灣大學 |
1994-10 |
A Test Clock Reduction Method for Scan-Designed Circuits
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Chang, J. S.; 林呈祥; Chang, J. S.; Lin, Chen-Shang |
Showing items 1-10 of 70 (7 Page(s) Totally)
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