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Taiwan Academic Institutional Repository >
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"lin chen shang"
Showing items 26-35 of 70 (7 Page(s) Totally)
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| 國立臺灣大學 |
1993 |
Test Time Reduction in Scan Designed Circuits
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Lai, W.; Kung, C.; 林呈祥; Lai, W.; Kung, C.; Lin, Chen-Shang |
| 國立臺灣大學 |
1993 |
超大型積體電路電腦輔助設計系統I-4:非同步電路
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林呈祥; Lin, Chen-Shang |
| 淡江大學 |
1992-11-26 |
Test set compaction for combinational circuits
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張昭憲; Chang, Jau-shien; 林呈祥; Lin, Chen-shang |
| 國立臺灣大學 |
1992-11 |
On the verification of state-coding in STGs
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Lin, Kuan- Jen; Lin, Chen-Shang |
| 國立臺灣大學 |
1992-11 |
Test set compaction for combinational circuits
|
Chang, Jau-Shien; Lin, Chen-Shang |
| 國立臺灣大學 |
1992-11 |
Test Reduction in Scan-Designed Circuits
|
Lai, W.; Kung, C.; 林呈祥; Lai, W.; Kung, C.; Lin, Chen-Shang |
| 國立臺灣大學 |
1992-11 |
Test Set Compaction for Combinational Circuits
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Chang, J.; 林呈祥; Chang, J.; Lin, Chen-Shang |
| 淡江大學 |
1992-06-01 |
On the OBDD-representation of general Boolean functions
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廖賀田; Liaw, Heh-tyan; Lin, Chen-shang |
| 國立臺灣大學 |
1992-03 |
A realization algorithm of asynchronous circuits from STG
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Lin, Kuan-Jen; Lin, Chen-Shang |
| 國立臺灣大學 |
1992-03 |
Parallel sequence fault simulation for synchronous sequential circuits
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Kung, Chen-Pin; Lin, Chen-Shang |
Showing items 26-35 of 70 (7 Page(s) Totally)
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View [10|25|50] records per page
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