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"lin geeng lih"的相關文件
顯示項目 1-8 / 8 (共1頁)
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| 國立交通大學 |
2017-04-21T06:49:29Z |
Stacked Low-Voltage PMOS for High-Voltage ESD Protection with Latchup-Free Immunity
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Tang, Kai-Neng; Liao, Seian-Feng; Ker, Ming-Dou; Chiou, Hwa-Chyi; Huang, Yeh-Jen; Tsai, Chun-Chien; Jou, Yeh-Ning; Lin, Geeng-Lih |
| 國立交通大學 |
2017-04-21T06:49:12Z |
ESD Protection Design with Latchup-Free Immunity in 120V SOI Process
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Huang, Yi-Jie; Ker, Ming-Dou; Huang, Yeh-Jen; Tsai, Chun-Chien; Jou, Yeh-Ning; Lin, Geeng-Lih |
| 國立交通大學 |
2017-04-21T06:49:05Z |
Impact of Guard Ring Layout on the Stacked Low-Voltage PMOS for High-Voltage ESD Protection
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Liao, Seian-Feng; Tang, Kai-Neng; Ker, Ming-Dou; Yeh, Jia-Rong; Chiou, Hwa-Chyi; Huang, Yeh-Jen; Tsai, Chun-Chien; Jou, Yeh-Ning; Lin, Geeng-Lih |
| 國立交通大學 |
2014-12-08T15:47:28Z |
Measurement on Snapback Holding Voltage of High-Voltage LDMOS for Latch-up Consideration
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Chen, Wen-Yi; Ker, Ming-Dou; Huang, Yeh-Jen; Jou, Yeh-Ning; Lin, Geeng-Lih |
| 國立交通大學 |
2014-12-08T15:25:06Z |
Experimental evaluation and device simulation of device structure influences on latchup immunity in high-voltage 40-V CMOS process
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Hsu, Sheng-Fu; Ker, Ming-Dou; Lin, Geeng-Lih; Jou, Yeh-Ning |
| 國立交通大學 |
2014-12-08T15:23:36Z |
Improvement on ESD Robustness of Lateral DMOS in High-Voltage CMOS ICs by Body Current Injection
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Chen, Wen-Yi; Ker, Ming-Dou; Jou, Yeh-Ning; Huang, Yeh-Jen; Lin, Geeng-Lih |
| 國立交通大學 |
2014-12-08T15:07:38Z |
The impact of high-voltage drift n-well and shallow trench isolation layouts on electrical characteristics of LDMOSFETs
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Huang, C. T.; Tsui, Bing-Yue; Liu, Hsu-Ju; Lin, Geeng-Lih |
| 義守大學 |
2009 |
Improvement on ESD robustness of lateral DMOS in high-voltage CMOS ICs by body current injection
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Chen, Wen-Yi ; Ker, Ming-Dou ; Jou, Yeh-Ning ; Huang, Yeh-Jen ; Lin, Geeng-Lih |
顯示項目 1-8 / 8 (共1頁)
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