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Showing items 1-10 of 16 (2 Page(s) Totally)
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| 國立彰化師範大學 |
2010-12 |
Combined Use of Rising and Falling Edge Triggered Clocks for Peak Current Reduction in IP-Based SoC/NoC Designs
|
Wu, Tsung-Yi; Kao, Tzi-Wei; Lin, How-Rern |
| 國立彰化師範大學 |
2010-01 |
Combined Use of Rising and Falling Edge Triggered Clocks for Peak Current Reduction in IP-Based SoC Designs
|
Wu, Tsung-Yi; Kao, Tzi-Wei; Huang, Shi-Yi; Li, Tai-Lun; Lin, How-Rern |
| 大葉大學 |
2009-05-25 |
A VLSI Design with Built-in SRAM Arrays for Implementing Full Search Block Matching Algorithm
|
Wu, Tsung-Yi;Lin, How-Rern;Chen, Kuang-Yao;Huang, Shi-Yi;Li, Tai-Lun |
| 大葉大學 |
2009-05-25 |
A Peak Current and Power Pad Count Reduction Tool for System-Level IC Designers
|
Wu, Tsung-Yi;Lin, How-Rern;Kao, Tzi-Wei;Huang, Shi-Yi;Li, Tai-Lun |
| 國立彰化師範大學 |
2009-05 |
A VLSI Design with Built-in SRAM Arrays for Implementing Full Search Block Matching Algorithm
|
Wu, Tsung-Yi; Chen, Kuang-Yao; Huang, Shi-Yi; Li, Tai-Lun; Lin, How-Rern |
| 國立彰化師範大學 |
2009-05 |
A Peak Current and Power Pad Count Reduction Tool for System-Level IC Designers
|
Wu, Tsung-Yi; Kao, Tzi-Wei; Huang, Shi-Yi; Li, Tai-Lun; Lin, How-Rern |
| 大葉大學 |
2009-04-1 |
A Conditional Isolation Technique for Low-Energy and High-Performance Wide Domino Gates
|
Lin, How-Rern;Chiu, Wei-Hao;Wu, Tsung-Yi |
| 大葉大學 |
2009-04-01 |
A Conditional Isolation Technique for Low-Energy and High-Performance Wide Domino Gates
|
Lin, How-Rern;Chiu, Wei-Hao;Wu, Tsung-Yi |
| 國立彰化師範大學 |
2009 |
A Conditional Isolation Technique for Low-Energy and High-Performance Wide Domino Gates
|
Lin, How-Rern; Chiu, Wei-Hao; Wu, Tsung-Yi |
| 大葉大學 |
2008-10 |
A Conditional Isolation Technique for Low-Energy and High-Performance Wide Domino Gates
|
Chiu, Wei-Hao;Lin, How-Rern |
Showing items 1-10 of 16 (2 Page(s) Totally)
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