|
English
|
正體中文
|
简体中文
|
Total items :0
|
|
Visitors :
52767994
Online Users :
696
Project Commissioned by the Ministry of Education
Project Executed by National Taiwan University Library
|
|
|
|
Taiwan Academic Institutional Repository >
Browse by Author
|
"lin how rern"
Showing items 1-16 of 16 (1 Page(s) Totally)
1
View [10|25|50] records per page
| 國立彰化師範大學 |
2010-12 |
Combined Use of Rising and Falling Edge Triggered Clocks for Peak Current Reduction in IP-Based SoC/NoC Designs
|
Wu, Tsung-Yi; Kao, Tzi-Wei; Lin, How-Rern |
| 國立彰化師範大學 |
2010-01 |
Combined Use of Rising and Falling Edge Triggered Clocks for Peak Current Reduction in IP-Based SoC Designs
|
Wu, Tsung-Yi; Kao, Tzi-Wei; Huang, Shi-Yi; Li, Tai-Lun; Lin, How-Rern |
| 大葉大學 |
2009-05-25 |
A VLSI Design with Built-in SRAM Arrays for Implementing Full Search Block Matching Algorithm
|
Wu, Tsung-Yi;Lin, How-Rern;Chen, Kuang-Yao;Huang, Shi-Yi;Li, Tai-Lun |
| 大葉大學 |
2009-05-25 |
A Peak Current and Power Pad Count Reduction Tool for System-Level IC Designers
|
Wu, Tsung-Yi;Lin, How-Rern;Kao, Tzi-Wei;Huang, Shi-Yi;Li, Tai-Lun |
| 國立彰化師範大學 |
2009-05 |
A VLSI Design with Built-in SRAM Arrays for Implementing Full Search Block Matching Algorithm
|
Wu, Tsung-Yi; Chen, Kuang-Yao; Huang, Shi-Yi; Li, Tai-Lun; Lin, How-Rern |
| 國立彰化師範大學 |
2009-05 |
A Peak Current and Power Pad Count Reduction Tool for System-Level IC Designers
|
Wu, Tsung-Yi; Kao, Tzi-Wei; Huang, Shi-Yi; Li, Tai-Lun; Lin, How-Rern |
| 大葉大學 |
2009-04-1 |
A Conditional Isolation Technique for Low-Energy and High-Performance Wide Domino Gates
|
Lin, How-Rern;Chiu, Wei-Hao;Wu, Tsung-Yi |
| 大葉大學 |
2009-04-01 |
A Conditional Isolation Technique for Low-Energy and High-Performance Wide Domino Gates
|
Lin, How-Rern;Chiu, Wei-Hao;Wu, Tsung-Yi |
| 國立彰化師範大學 |
2009 |
A Conditional Isolation Technique for Low-Energy and High-Performance Wide Domino Gates
|
Lin, How-Rern; Chiu, Wei-Hao; Wu, Tsung-Yi |
| 大葉大學 |
2008-10 |
A Conditional Isolation Technique for Low-Energy and High-Performance Wide Domino Gates
|
Chiu, Wei-Hao;Lin, How-Rern |
| 大葉大學 |
2006-08 |
Low-Power High-Speed Design Technique for High Fan-in Domino Gates
|
Chiu, Wei-Hao;Lin, How-Rern |
| 大葉大學 |
2006-04 |
Conditional Isolator Technique for Wide Fan-in Pseudo-Footless Domino Logic Circuits
|
Chiu, Wei-Hao;Lin, How-Rern |
| 國立高雄第一科技大學 |
2005.11 |
應用於低電壓保護功能之脈波寬度調變驅動晶片之設計
|
吳在寧;郭永超;林浩仁; Wu, Tsai-Ning;Kuo, Yeong-Chau;Lin, How-Rern |
| 大葉大學 |
2004-11 |
Conditional Isolator Technique for Wide Pseudo-Footless Domino Logic Circuits
|
;Lin, How-Rern |
| 大葉大學 |
2004-03 |
On Concerning Destination Movement in Path Maintenance for Ad Hoc On-Demand Routing
|
;Lin, How-Rern |
| 大葉大學 |
2002-03 |
On Concerning Destination Movement in Path Maintenance for Ad Hoc On-Demand RoutingMobile Computing 2002 The 8th Mobile Computing workshoppp
|
;Lin, How-Rern |
Showing items 1-16 of 16 (1 Page(s) Totally)
1
View [10|25|50] records per page
|
