|
English
|
正體中文
|
简体中文
|
总笔数 :0
|
|
造访人次 :
53107332
在线人数 :
1032
教育部委托研究计画 计画执行:国立台湾大学图书馆
|
|
|
"lin ing chao"的相关文件
显示项目 1-10 / 12 (共2页)
1 2 > >>
每页显示[10|25|50]项目
| 國立成功大學 |
2016-07 |
Reducing Aging Effects on Ternary CAM
|
Lin, Ing-Chao; Lee, Yen-Han; Wang, Sheng-Wei |
| 國立成功大學 |
2015-11-13 |
Electronic device having scratchpad memory and management method for scratchpad memory
|
Chang, Ta-Wei;Lin, Ing-Chao;Su, Wen-Yu;Chien, Yu-Shiang |
| 國立成功大學 |
2015-10 |
High-Endurance Hybrid Cache Design in CMP Architecture With Cache Partitioning and Access-Aware Policies
|
Lin, Ing-Chao; Chiou, Jeng-Nian |
| 國立成功大學 |
2015-09 |
High-Performance Low-Power Carry Speculative Addition With Variable Latency
|
Lin, Ing-Chao; Yang, Yi-Ming; Lin, Cheng-Chian |
| 國立交通大學 |
2015-07-21T11:20:26Z |
BTI-Aware Sleep Transistor Sizing Algorithm for Reliable Power Gating Designs
|
Wu, Kai-Chiang; Lin, Ing-Chao; Wang, Yao-Te; Yang, Shuen-Shiang |
| 國立成功大學 |
2015-03 |
Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic
|
Lin, Ing-Chao; Cho, Yu-Hung; Yang, Yi-Ming |
| 國立成功大學 |
2014-12 |
CASA: Contention-Aware Scratchpad Memory Allocation for Online Hybrid On-Chip Memory Management
|
Chang, Da-Wei; Lin, Ing-Chao; Chien, Yu-Shiang; Lin, Chin-Lun; Su, Alvin W. -Y.; Young, Chung-Ping |
| 國立成功大學 |
2014-10 |
BTI-Aware Sleep Transistor Sizing Algorithm for Reliable Power Gating Designs
|
Wu, Kai-Chiang; Lin, Ing-Chao; Wang, Yao-Te; Yang, Shuen-Shiang |
| 國立成功大學 |
2014-09 |
NBTI Tolerance and Leakage Reduction Using Gate Sizing
|
Lin, Ing-Chao; Syu, Shun-Ming; Ho, Tsung-Yi |
| 國立成功大學 |
2014-09 |
NBTI and Leakage Reduction Using ILP-Based Approach
|
Lin, Ing-Chao; Li, Kuan-Hui; Lin, Chia-Hao; Wu, Kai-Chiang |
显示项目 1-10 / 12 (共2页)
1 2 > >>
每页显示[10|25|50]项目
|
