|
English
|
正體中文
|
简体中文
|
總筆數 :0
|
|
造訪人次 :
53269668
線上人數 :
917
教育部委託研究計畫 計畫執行:國立臺灣大學圖書館
|
|
|
"lin jai ming"的相關文件
顯示項目 1-10 / 25 (共3頁)
1 2 3 > >>
每頁顯示[10|25|50]項目
| 臺大學術典藏 |
2018-09-10T07:03:51Z |
Graph matching-based algorithms for FPGA segmentation design
|
YAO-WEN CHANG; Wong, D.F.; Lin, Jai-Ming; Chang, Yao-Wen |
| 臺大學術典藏 |
2018-09-10T04:12:52Z |
Performance-driven placement for dynamically reconfigurable FPGAs
|
Wu, G.-M.; Lin, J.-M.; Chang, Y.-W.; Wu, Guang-Ming; Lin, Jai-Ming; Chang, Yao-Wen; YAO-WEN CHANG |
| 國立成功大學 |
2016-10 |
An Efficient and Effective Methodology to Control Turn-On Sequence of Power Switches for Power Gating Designs
|
Shyu, Ya-Ting; Lin, Jai-Ming; Lin, Che-Chun; Huang, Chun-Po; Chang, Soon-Jyh |
| 國立成功大學 |
2016-05 |
A Systematic Design Methodology of Asynchronous SAR ADCs
|
Huang, Chun-Po; Lin, Jai-Ming; Shyu, Ya-Ting; Chang, Soon-Jyh |
| 國立成功大學 |
2015-05 |
Placement Density Aware Power Switch Planning Methodology for Power Gating Designs
|
Lin, Jai-Ming; Lin, Che-Chun |
| 國立交通大學 |
2014-12-12T02:18:50Z |
現場可程式化邏輯閘陣列導線段之設計
|
林家民; Lin, Jai-Ming; 張耀文; Yao-Wen Chang |
| 國立成功大學 |
2014-11 |
F-FM: Fixed-Outline Floorplanning Methodology for Mixed-Size Modules Considering Voltage-Island Constraint
|
Lin, Jai-Ming; Wu, Ji-Heng |
| 國立成功大學 |
2013-04 |
Effective and Efficient Approach for Power Reduction by Using Multi-Bit Flip-Flops
|
Shyu, Ya-Ting; Lin, Jai-Ming; Huang, Chun-Po; Lin, Cheng-Wu; Lin, Ying-Zu; Chang, Soon-Jyh |
| 國立成功大學 |
2012-12 |
Mismatch-Aware Common-Centroid Placement for Arbitrary-Ratio Capacitor Arrays Considering Dummy Capacitors
|
Lin, Cheng-Wu; Lin, Jai-Ming; Chiu, Yen-Chih; Huang, Chun-Po; Chang, Soon-Jyh |
| 國立成功大學 |
2012-03 |
SKB-Tree: A Fixed-Outline Driven Representation for Modern Floorplanning Problems
|
Lin, Jai-Ming; Hung, Zhi-Xiong |
顯示項目 1-10 / 25 (共3頁)
1 2 3 > >>
每頁顯示[10|25|50]項目
|
