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"lin kh"
Showing items 66-75 of 267 (27 Page(s) Totally)
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| 國立交通大學 |
2014-12-08T15:45:47Z |
Thin-film transistors with polycrystalline silicon films prepared by two-step rapid thermal annealing
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Cheng, HC; Huang, CY; Wang, FS; Lin, KH; Tarntair, FG |
| 國立交通大學 |
2014-12-08T15:38:45Z |
Design on ESD protection scheme for IC with power-down-mode operation
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Ker, MD; Lin, KH |
| 國立交通大學 |
2014-12-08T15:38:37Z |
Double snapback characte'ristics in high-voltage nMOSFETs and the impact to on-chip ESD protection design
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Ker, MD; Lin, KH |
| 國立交通大學 |
2014-12-08T15:38:30Z |
On-chip ESD protection design with substrate-triggered technique for mixed-voltage I/O circuits in subquarter-micrometer CMOS process
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Ker, MD; Lin, KH; Chuang, CH |
| 國立交通大學 |
2014-12-08T15:26:21Z |
MOS-bounded diodes for on-chip ESD protection in a 0.15-mu m shallow-trench-isolation salicided CMOS process
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Ker, MD; Lin, KH; Chuang, CH |
| 國立交通大學 |
2014-12-08T15:19:40Z |
MOS-bounded diodes for on-chip ESD protection in deep submicron CMOS process
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Ker, MD; Lin, KH; Chuang, CH |
| 國立交通大學 |
2014-12-08T15:18:41Z |
The impact of low-holding-voltage issue in high-voltage CMOS technology and the design of latchup-free power-rail ESD clamp circuit for LCD driver ICs
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Ker, MD; Lin, KH |
| 國立交通大學 |
2014-12-08T15:18:37Z |
Low threshold and high power output of a diode-pumped nonlinear mirror mode-locked Nd : GdVO4 laser
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Lin, JH; Yang, WH; Hsieh, WF; Lin, KH |
| 國立交通大學 |
2014-12-08T15:18:07Z |
ESD protection design for I/O cells with embedded SCR structure as power-rail ESD clamp device in nanoscale CMOS technology
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Ker, MD; Lin, KH |
| 國立交通大學 |
2014-12-08T15:17:36Z |
Multistability in recurrent neural networks
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Cheng, CY; Lin, KH; Shih, CW |
Showing items 66-75 of 267 (27 Page(s) Totally)
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