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"lin ye jyun"的相關文件
顯示項目 1-7 / 7 (共1頁)
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| 臺大學術典藏 |
2020-05-04T07:48:21Z |
System-Level Performance and Power Optimization for MPSoC: A Memory Access-Aware Approach
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Lin, Ye-Jyun;Yang, Chia-Lin;Huang, Jiao-We;Lin, Tay-Jyi;Hsueh, Chih-Wen;Chang, Naehyuck; Lin, Ye-Jyun; Yang, Chia-Lin; Huang, Jiao-We; Lin, Tay-Jyi; Hsueh, Chih-Wen; Chang, Naehyuck; CHIH-WEN HSUEH |
| 臺大學術典藏 |
2020-05-04T07:27:48Z |
Hierarchical memory scheduling for multimedia MPSoCs.
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Lin, Ye-Jyun;Yang, Chia-Lin;Lin, Tay-Jyi;Huang, Jiao-Wei;Chang, Naehyuck; Lin, Ye-Jyun; Yang, Chia-Lin; Lin, Tay-Jyi; Huang, Jiao-Wei; Chang, Naehyuck; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:46Z |
Memory access aware power gating for MPSoCs.
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Lin, Ye-Jyun; Lin, Ye-Jyun;Yang, Chia-Lin;Huang, Jiao-Wei;Chang, Naehyuck; Yang, Chia-Lin; Huang, Jiao-Wei; Chang, Naehyuck; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:45Z |
A buffer cache architecture for smartphones with hybrid DRAM/PCM memory.
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CHIA-LIN YANG; Wang, Cheng-Yuan Michael; Li, Hsiang-Pang; Yang, Chia-Lin; Lin, Ye-Jyun; Lin, Ye-Jyun;Yang, Chia-Lin;Li, Hsiang-Pang;Wang, Cheng-Yuan Michael |
| 臺大學術典藏 |
2018-09-10T07:00:35Z |
Tunablevp: a tunable virtual platform for easy soc design space exploration
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Lin, Ye-Jyun; Chen, Yi-Jung; Huang, Chin-Chie; Lin, Tzu-Ching; Chi, Jaw-Wei; Yang, Chia-Lin; CHIA-LIN YANG |
| 國立臺灣大學 |
2015 |
系統層級智慧型個人裝置記憶體與儲存子系統效能功耗最佳化
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林業峻; Lin, Ye-Jyun |
| 國立臺灣大學 |
2008 |
TunableVP: A Tunable Virtual Platform for Easy SoC Design Space Exploration
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Lin, Ye-Jyun; Chen, Yi-Jung; Huang, Chin-Chie; Lin, Tzu-Ching; Chi, Jaw-Wei; Yang, Chia-Lin |
顯示項目 1-7 / 7 (共1頁)
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每頁顯示[10|25|50]項目
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