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教育部委託研究計畫      計畫執行:國立臺灣大學圖書館
 
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機構 日期 題名 作者
國立交通大學 2020-05-05T00:02:00Z Achieving Routing Integrity in Analog Layout Migration via Cartesian Detection Lines Chen, Hung-Ming; Liu, Chien-Nan Jimmy; Hung, Chia-Hao; Lin, Zi-Jun; Chi, Hao-Yu
國立交通大學 2020-02-02T23:55:33Z A Structure-Based Methodology for Analog Layout Generation Chen, Yu-Hsien; Chi, Hao-Yu; Song, Ling-Yen; Liu, Chien-Nan Jimmy; Chen, Hung-Ming
國立交通大學 2019-04-02T06:04:44Z Estimation of loss coefficients of Nonlinear rubber using iterative H-infinity filter Chih-Hu Wang; Lee, Bore-Kuen; Wei-Hang Tseng; Chung-Hsi Fu; Chauchin Su; Liu, Chien-Nan Jimmy
國立交通大學 2019-04-02T06:04:43Z H-infinity output feedback control of stochastic T-S fuzzy model with state-dependent noise Ho, Shih-Ju; Wang, Chih-Hu; Lee, Bore-Kuen; Su, Chauchin; Liu, Chien-Nan Jimmy
國立交通大學 2018-08-21T05:57:09Z Performance-Preserved Analog Routing Methodology via Wire Load Reduction Chi, Hao-Yu; Tseng, Hwa-Yi; Liu, Chien-Nan Jimmy; Chen, Hung-Ming
國立交通大學 2017-04-21T06:49:40Z Package Routability- and IR-Drop-Aware Finger/Pad Assignment in Chip-Package Co-Design Lu, Chao-Hung; Chen, Hung-Ming; Liu, Chien-Nan Jimmy; Shih, Wen-Yu
國立交通大學 2017-04-21T06:49:07Z On increasing signal integrity with minimal decap insertion in area-array SoC floorplan design Lu, Chao-Hung; Chen, Hung-Ming; Liu, Chien-Nan Jimmy
國立交通大學 2014-12-08T15:38:08Z Design Planning with 3D-Via Optimization in Alternative Stacking Integrated Circuits Lu, Chao-Hung; Chen, Hung-Ming; Liu, Chien-Nan Jimmy
國立交通大學 2014-12-08T15:31:26Z Package routability- and IR-drop-aware finger/pad planning for single chip and stacking IC designs Lu, Chao-Hung; Chen, Hung-Ming; Liu, Chien-Nan Jimmy; Shih, Wen-Yu
國立交通大學 2014-12-08T15:25:28Z An observability measure to enhance statement coverage metric for proper evaluation of verification completeness Jiang, Tai-Ying; Liu, Chien-Nan Jimmy; Jou, Jing-Yang

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