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Showing items 1-11 of 11 (1 Page(s) Totally)
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| 國立交通大學 |
2014-12-08T15:45:10Z |
An automatic controller extractor for HDL descriptions at the RTL
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Liu, CNJ; Jou, JY |
| 國立交通大學 |
2014-12-08T15:41:17Z |
A design-for-verification technique for functional pattern reduction
|
Liu, CNJ; Chen, IL; Jou, JY |
| 國立交通大學 |
2014-12-08T15:40:33Z |
An efficient power model for IP-level complex designs
|
Hsu, CY; Liu, CNJ; Jou, JY |
| 國立交通大學 |
2014-12-08T15:37:24Z |
Efficient vector compaction methods for power estimation with consecutive sampling techniques
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Hsu, CY; Liu, CNJ; Jou, JY |
| 國立交通大學 |
2014-12-08T15:26:58Z |
A novel approach for functional coverage measurement in HDL
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Liu, CNJ; Chang, CY; Jou, JY; Lai, MC; Juan, HM |
| 國立交通大學 |
2014-12-08T15:26:51Z |
Automatic functional vector generation using the interacting FSM model
|
Liu, CNJ; Yen, CC; Jou, JY |
| 國立交通大學 |
2014-12-08T15:26:45Z |
An efficient design-for-verification technique for HDLs
|
Liu, CNJ; Chen, IL; Jou, JY |
| 國立交通大學 |
2014-12-08T15:26:28Z |
Effective error diagnosis for RTL designs in HDLS
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Jiang, TY; Liu, CNJ; Jou, JY |
| 國立交通大學 |
2014-12-08T15:26:21Z |
Improved vector compaction for power estimation with multi-sequence sampling technique
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Hsu, CY; Liu, CNJ; Jou, JY |
| 國立交通大學 |
2014-12-08T15:26:11Z |
An efficient IP-Level power model for complex digital circuits
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Hsu, CY; Liu, CNJ; Jou, JY |
| 國立交通大學 |
2014-12-08T15:25:24Z |
Estimating likelihood of correctness for error candidates to assist debugging faulty HDL designs
|
Jiang, TY; Liu, CNJ; Jou, JY |
Showing items 1-11 of 11 (1 Page(s) Totally)
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