|
Taiwan Academic Institutional Repository >
Browse by Author
|
"liu cw"
Showing items 21-30 of 73 (8 Page(s) Totally) << < 1 2 3 4 5 6 7 8 > >> View [10|25|50] records per page
國立交通大學 |
2014-12-08T15:26:47Z |
Novel strategies of FSG-CMP for within-wafer uniformity improvement and wafer edge yield enhancement beyond 0.18 micro technologies
|
Chen, KW; Wang, YL; Chang, L; Liu, CW; Lin, YK; Wang, TC; Chang, ST; Lo, KY |
國立交通大學 |
2014-12-08T15:25:52Z |
Novel programmable digital signal processor for multimedia applications
|
Lin, LC; Lin, TJ; Lee, CC; Chao, CM; Chen, SK; Liu, CH; Hsiao, PC; Liu, CW; Jen, CW |
國立交通大學 |
2014-12-08T15:25:52Z |
Complexity-aware design of DA-based fir filters
|
Chen, CC; Lin, TJ; Liu, CW; Jen, CW |
國立交通大學 |
2014-12-08T15:25:38Z |
Lightweight arithmetic units for VLSI digital signal processors
|
Ou, SH; Lin, TJ; Lin, HY; Chao, CM; Liu, CW; Jen, CW |
國立交通大學 |
2014-12-08T15:25:38Z |
A novel register organization for VLIW digital signal processors
|
Lin, TJ; Lee, CC; Liu, CW; Jen, CW |
國立交通大學 |
2014-12-08T15:25:37Z |
Architecture for area-efficient 2-D transform in H.264/AVC
|
Kuo, YT; Lin, TY; Liu, CW; Jen, CW |
國立交通大學 |
2014-12-08T15:25:25Z |
A dynamic normalization technique for decoding LDPC codes
|
Liao, YC; Lin, CC; Liu, CW; Chang, HC |
國立交通大學 |
2014-12-08T15:25:24Z |
Hierarchical instruction encoding for VLIW digital signal processors
|
Liu, CH; Lin, TJ; Chao, CM; Hsiao, PC; Lin, LC; Chen, SK; Huang, CW; Liu, CW; Jen, CW |
國立交通大學 |
2014-12-08T15:25:23Z |
Pipelining technique for energy-aware datapaths
|
Huang, WS; Lin, TJ; Ou, SH; Liu, CW; Jen, CW |
國立交通大學 |
2014-12-08T15:17:31Z |
A compact DSP core with static floating-point arithmetic
|
Lin, TJ; Lin, HY; Chao, CM; Liu, CW; Jen, CW |
Showing items 21-30 of 73 (8 Page(s) Totally) << < 1 2 3 4 5 6 7 8 > >> View [10|25|50] records per page
|