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Showing items 41-50 of 70 (7 Page(s) Totally)
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| 國立臺灣科技大學 |
2015 |
Electrical interconnect test of 3D ICs made of dies without ESD protection circuits with a built-in test circuit
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Nanbara, K.;Odoriba, A.;Hashizume, M.;Yotsuyanagi, H.;Lu, S.-K. |
| 國立臺灣科技大學 |
2015 |
A testable design for electrical interconnect tests of 3D ICs
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Odoriba, A.;Umezu, S.;Hashizume, M.;Yotsuyanagi, H.;Ali, F.A.B.;Lu, S.-K. |
| 國立臺灣科技大學 |
2015 |
An enhanced built-in self-repair technique for yield and reliability improvement of embedded memories
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Lu, S.-K;Lin, H.-W;Hashizume, M. |
| 國立臺灣科技大學 |
2015 |
Electrical interconnect test method of 3D ICs without boundary scan flip flops
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Hashizume, M;Umezu, S;Ikiri, Y;Ali, F.A.B;Yotsuyanagi, H;Lu, S.-K. |
| 國立臺灣科技大學 |
2014 |
A power saving mechanism for multimedia streaming services in cloud computing
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Ma, Y.-W.;Chen, J.-L.;Chou, C.-H.;Lu, S.-K. |
| 國立臺灣科技大學 |
2013 |
Testable design for electrical testing of open defects at interconnects in 3D ICs
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Hashizume, M.;Konishi, T.;Yotsuyanag, H.;Lu, S.-K. |
| 國立臺灣科技大學 |
2013 |
Error-tolerance evaluation and design techniques for motion estimation computing arrays
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Lu, S.-K.;Chen, M.-C.;Chen, Y.-C. |
| 國立臺灣科技大學 |
2013 |
Efficient test and repair architectures for 3D TSV-based random access memories
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Lu, S.-K.;Lu, U.-C.;Pong, S.-W.;Cheng, H.-C. |
| 國立臺灣科技大學 |
2013 |
Reduction method of number of electromagnetic simulation times for estimating output voltage at hard open TSV in 3D IC
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Haraguchi, E.;Hashizume, M.;Manabe, K.;Yotsuyanagi, H.;Tada, T.;Lu, S.-K.;Roth, Z. |
| 國立臺灣科技大學 |
2013 |
Built-in IDDT appearance time sensor for detecting open faults in 3D IC
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Suenaga, S.;Hashizume, M.;Yotsuyanagi, H.;Tada, T.;Lu, S.-K. |
Showing items 41-50 of 70 (7 Page(s) Totally)
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