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教育部委託研究計畫 計畫執行:國立臺灣大學圖書館
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"luo shien chun"的相關文件
顯示項目 1-5 / 5 (共1頁)
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| 國立交通大學 |
2016-03-28T00:05:45Z |
A 0.48V 0.57nJ/Pixel Video-Recording SoC in 65nm CMOS
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Lin, Tay-Jyi; Chien, Cheng-An; Chang, Pei-Yao; Chen, Ching-Wen; Wang, Po-Hao; Shyu, Ting-Yu; Chou, Chien-Yung; Luo, Shien-Chun; Guo, Jiun-In; Chen, Tien-Fu; Chuang, Gene C. H.; Chu, Yuan-Hua; Cheng, Liang-Chia; Su, Hong-Men; Jou, Chewnpu; Ieong, Meikei; Wu, Cheng-Wen; Wang, Jinn-Shyan |
| 國立交通大學 |
2015-07-21T11:20:29Z |
Separate Clock Network Voltage for Correcting Random Errors in ULV Clocked Storage Cells
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Luo, Shien-Chun; Chang, Kuo-Chiang; Chen, Ming-Pin; Huang, Ching-Ji; Chiu, Yi-Fang; Chen, Po-Hsun; Cheng, Liang-Chia; Liu, Chih-Wei; Chu, Yuan-Hua |
| 國立交通大學 |
2015-07-21T08:31:16Z |
An Ultra-Low Voltage Hearing Aid Chip using Variable-Latency Design Technique
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Chang, Kuo-Chiang; Luo, Shien-Chun; Huang, Ching-Ji; Liu, Chih-Wei; Chu, Yuan-Hua; Jou, Shyh-Jye |
| 國立成功大學 |
2011-09-02 |
超低功率並具有製程變異意識之電路與儲存元件設計
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羅賢君; Luo, Shien-Chun |
| 國立成功大學 |
2009-11 |
Energy-Efficient Dual-Edge-Triggered Level Converting Flip Flops With Symmetry in Setup Times and Insensitivity to Output Parasitics
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Chiou, Lih-Yih; Luo, Shien-Chun |
顯示項目 1-5 / 5 (共1頁)
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