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Institution Date Title Author
臺大學術典藏 2018-09-10T06:34:59Z Triple-Threshold Static Power Minimization Technique in High-Level Synthesis for Designing High-Speed Low-Power SOC Applications Using 90nm MTCMOS Technology H. I. Chen;E. K. Loo;J. B. Kuo;M. J. Syrzycki; H. I. Chen; E. K. Loo; J. B. Kuo; M. J. Syrzycki; JAMES-B KUO
臺大學術典藏 2018-09-10T06:34:59Z Triple-Threshold Static Power Minimization Technique in High-Level Synthesis for Designing High-Speed Low-Power SOC Applications Using 90nm MTCMOS Technology H. I. Chen;E. K. Loo;J. B. Kuo;M. J. Syrzycki; H. I. Chen; E. K. Loo; J. B. Kuo; M. J. Syrzycki; JAMES-B KUO

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