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Institution Date Title Author
亞洲大學 1995-02 On the Construction of a Prolog-Based Verifier for Systolic Designs Timothy K. Shih; Nam Ling; Ruth Davis; Fuyau Lin
亞洲大學 1994-04 A Temporal Arithmetic Based Reasoning System for Systolic Array Designs Timothy K. Shih ; Nam Ling
亞洲大學 1993 The Use of Fixed Point Induction in Verifying Systolic Array Designs: An Applicative Approach Nam Ling; Jonathan Huang; Timothy K. Shih
亞洲大學 1993 VSTA: A Prolog-based Formal Verifier for Systolic Array Designs Nam Ling;Timothy K. Shih
亞洲大學 1992 A Temporal Rule-Based Expert System for Systolic Array Designs Timothy K. Shih; Nam Ling; Xi Chen
亞洲大學 1992 Inductive Techniques for Formal Verification of Systolic Array Designs in DSP Applications Nam Ling; Timothy K. Shih; Jonathan Huang
亞洲大學 1992 An Automatic Design Specification and Verification Tool for Systolic Architecture Timothy K. Shih; Nam Ling; Ruth Davis; Fuyau Lin
亞洲大學 1991 Verification Tools for Systolic Array Design Fuyau Lin; Timothy K. Shih; Nam Ling
亞洲大學 1991 Axiomatic Approach for Systolic Array Design Fuyau Lin; Timothy K. Shih;Nam Ling
亞洲大學 1991 Automatic Formal Verification of Systolic Array Designs Nam Ling; Fuyau Lin; Timothy K. Shih;Ruth Davis

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