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Institution Date Title Author
臺大學術典藏 2018-09-10T07:41:35Z A CMOS Semi-Static Latch Circuit without Charge Sharing and Leakage Current Problems P. F. Lin; J. B. Kuo; JAMES-B KUO
臺大學術典藏 2018-09-10T04:15:05Z A 0.8-V 128-Kb Four-Way Set-Associative Two-Level CMOS Cache Memory Using Two-Stage Wordline/Bitline-Oriented Tag-Compare (WLOTC/BLOTC) Scheme P. F. Lin; J. B. Kuo; JAMES-B KUO
臺大學術典藏 2018-09-10T03:50:14Z A 1-V 128-kb four-way set-associative CMOS cache memory using wordline-oriented tag-compare (WLOTC) structure with the content-addressable-memory (CAM) 10-transistor tag cell P. F. Lin; J. B. Kuo; P. F. Lin; J. B. Kuo; JAMES-B KUO
臺大學術典藏 2018-09-10T03:50:14Z A 1-V 128-kb four-way set-associative CMOS cache memory using wordline-oriented tag-compare (WLOTC) structure with the content-addressable-memory (CAM) 10-transistor tag cell P. F. Lin; J. B. Kuo; P. F. Lin; J. B. Kuo; JAMES-B KUO

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