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"rau jiann chyi"
Showing items 26-35 of 44 (5 Page(s) Totally)
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| 淡江大學 |
2006-05 |
A broadcast-based test scheme for reducing test size and application time
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Rau, Jiann-chyi; Chang, Jun-yi; Chen, Chien-shiun |
| 淡江大學 |
2005-05-23 |
Reconfigurable multiple scan-chains for reducing test application time of SOCs
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Rau, Jiann-chyi; Chien, Chih-lung; Ma, Jia-shing |
| 淡江大學 |
2005-05-23 |
A novel reseeding mechanism for pseudo-random testing of VLSI circuits
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Rau, Jiann-chyi; Ho, Ying-fu; Wu, Po-han |
| 淡江大學 |
2004-11 |
An Efficient Low-Overhead Policy for Constructing Multiple Scan-Chains
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Rau, Jiann-Chyi; Lin, Ching-Hsiu; Chang, Jun-Yi |
| 淡江大學 |
2004-07 |
以Layout為基礎的高效率多重掃描鍊最佳化
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饒建奇; Rau, Jiann-chyi |
| 淡江大學 |
2004-05 |
An Efficient Multi-Scan-Chain Optimization Using Physical Layout Information
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Rau, Jiann-chyi; Lin, Ching-hsiu; Chang, Jun-yi |
| 淡江大學 |
2004-05 |
Built-In Reseeding With Modifying Technique For Bist
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Rau, Jiann-chyi; Yang, Ta-wei; Ho, Ying-fu |
| 淡江大學 |
2004-05 |
The optimal testrail architecture for core-based soc testing
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Rau, Jiann-chyi; Huang, Wang-tiao; Chien, Chih-lung |
| 淡江大學 |
2004 |
An Efficient Low-Overhead Policy for Constructing Multiple Scan-Chains
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Rau, Jiann-chyi; Lin, Ching-hsiu; Chang, Jun-yi |
| 淡江大學 |
2004 |
The Optimal Layout-Based Multi-Scan-Chain Scheme
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Rau, Jiann-chyi; Lin, Ching-hsiu; Chang, Jun-yi |
Showing items 26-35 of 44 (5 Page(s) Totally)
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