| 淡江大學 |
2004-05 |
An Efficient Multi-Scan-Chain Optimization Using Physical Layout Information
|
Rau, Jiann-chyi; Lin, Ching-hsiu; Chang, Jun-yi |
| 淡江大學 |
2004-05 |
Built-In Reseeding With Modifying Technique For Bist
|
Rau, Jiann-chyi; Yang, Ta-wei; Ho, Ying-fu |
| 淡江大學 |
2004-05 |
The optimal testrail architecture for core-based soc testing
|
Rau, Jiann-chyi; Huang, Wang-tiao; Chien, Chih-lung |
| 淡江大學 |
2004 |
An Efficient Low-Overhead Policy for Constructing Multiple Scan-Chains
|
Rau, Jiann-chyi; Lin, Ching-hsiu; Chang, Jun-yi |
| 淡江大學 |
2004 |
The Optimal Layout-Based Multi-Scan-Chain Scheme
|
Rau, Jiann-chyi; Lin, Ching-hsiu; Chang, Jun-yi |
| 淡江大學 |
2004 |
An Efficient Reseeding With Modifying Technique for Pseudo-Random-Based BIST
|
Rau, Jiann-chyi; Yang, Ta-wei; Ho, Ying-fu |
| 淡江大學 |
2003-08 |
A Datapath-Based Debugging Mechanism for RTL Description
|
Rau, Jiann-Chyi; Chang, Yi-Yuan; Huang, Wang-Tiao |
| 淡江大學 |
2003-08 |
Pseudo-Exhaustively Testing VLSI Circuits Using Enhanced Tree-Structured Scan Chains
|
Rau, Jiann-Chyi; Kuo, Kuo-Chun; Yang, Ta-Wei |
| 淡江大學 |
2003-08 |
A Core-Based Test Methodology for Fast Multipliers
|
Rau, Jiann-Chyi; Lin, Chia-Hung; Lin, Ching-Hsiu |
| 淡江大學 |
2003 |
An Efficient Test Strategy for Fast Multiplier Cores
|
Rau, Jiann-chyi; Lin, Chia-hung; Lin, Ching-hsiu |
| 淡江大學 |
2002-08 |
A Novel BIST Response Analyzer Based on TLS
|
Rau, Jiann-Chyi; Jone, Wen-Ben |
| 淡江大學 |
2001-08 |
The methods to construct imaging circuit for efficient VLSI circuit verification
|
饒建奇; Rau, Jiann-chyi; Chen, Y. M.; Chang, S. C. |
| 淡江大學 |
2001-01 |
A timing driven pseudo exhaustive testing for VLSI circuits
|
Chang, Shih-chieh; 饒建奇; Rau, Jiann-chyi |
| 淡江大學 |
2000-10 |
Tree-Structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuits
|
Rau, Jiann-chyi; Jone, W.B.; Chang, S.C.; Wu, Y.L. |
