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Showing items 1-10 of 44 (5 Page(s) Totally)
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| 淡江大學 |
2021-11-16 |
A Scan-Based Lower-Power Testing Architecture for Modern Circuits
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Rau, Jiann-Chyi;Wang, Jia-Xiang |
| 淡江大學 |
2018-04-13 |
Low-Capture-Power X-filling Method Base On Architecture Using Selection Expansion
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Chung, Yu-Ting;Rau, Jiann-Chyi |
| 淡江大學 |
2013-06 |
Compact Test Pattern Selection for Small Delay Defect
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Chia-Yuan Chang; Kuan-Yu Liao; Sheng-Chang Hsu; Li, J.C.; Rau, Jiann-Chyi |
| 淡江大學 |
2012-11 |
Optimal Unknown Bit Filtering for Test Response Masking
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Weng, Ding-ke; Rau, Jiann-Chyi; Lin , Cheng-han |
| 淡江大學 |
2012-11 |
An Efficient Test Data Compression Scheme Using Selection Expansion
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Rau, Jiann-chyi |
| 淡江大學 |
2012-11 |
Multimode ATPG for DVFS Designs
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Bai, B.; Lin, J.; Rau, Jiann-chyi |
| 淡江大學 |
2012-10-18 |
Thermal-Aware Test Schedule and TAM Co-Optimization for Three-Dimensional IC
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Shih, Chi-Jih; Hsu, Chih-Yao; Kuo, Chun-Yi; Li, James; Rau, Jiann-Chyi; Krishnendu Chakrabarty |
| 淡江大學 |
2012-06 |
Test Slice Difference Technique for Low-Transition Test Data Compression
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Rau, Jiann-Chyi; Wu, Po-Han; Li, Wei-Lin |
| 淡江大學 |
2011-06 |
Power-aware compression scheme for multiple scan-chain
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Rau, Jiann-Chyi; Wu, Po-Han |
| 淡江大學 |
2011-03 |
An Efficient Algorithm to Selectively Gate Scan Cells for Capture Power Reduction
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Rau, Jiann-Chyi; Wu, Chung-Lin; Wu, Po-Han |
Showing items 1-10 of 44 (5 Page(s) Totally)
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