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"ruan s j"
Showing items 51-60 of 115 (12 Page(s) Totally)
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| 東海大學 |
2013-03-04 |
A low power detection routing method for bufferless NoC
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Hsu, C.-K.; Tsai, K.-L.; Jheng, J.-F.; Ruan, S.-J.; Shen, C.-A. |
| 國立臺灣科技大學 |
2013 |
Histogram shrinking for power-saving contrast enhancement
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Peng, Y.-T.;Cheng, F.-C.;Jan, L.-M.;Ruan, S.-J. |
| 國立臺灣科技大學 |
2013 |
Configurable redundant via-aware standard cell design considering multi-via mechanism
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Kan, T.-C.;Hong, H.-M.;Chen, Y.-J.;Ruan, S.-J. |
| 國立臺灣科技大學 |
2013 |
A low power detection routing method for bufferless NoC
|
Hsu, C.-K.;Tsai, K.-L.;Jheng, J.-F.;Ruan, S.-J.;Shen, C.-A. |
| 國立臺灣科技大學 |
2013 |
Reliability consideration with rectangle- and double-signal through silicon vias insertion in 3D thermal-aware floorplanning
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Hsu, C.-H.;Ruan, S.-J.;Chen, Y.-J.;Kan, T.-C. |
| 國立臺灣科技大學 |
2013 |
A Sub-Image Edge Preservation method for histogram equalization
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Peng, Y.-T.;Tsai, B.-C.;Ruan, S.-J. |
| 國立臺灣科技大學 |
2013 |
Cluster-based thermal-aware 3D-floorplanning technique with post-floorplan TTSV insertion at via-channels
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Wen, C.-C.;Chen, Y.-J.;Ruan, S.-J. |
| 國立臺灣科技大學 |
2013 |
Design of a practical nanometer-scale redundant via-aware standard cell library for improved redundant via1 insertion rate
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Kan, T.-C.;Yang, S.-H.;Chang, T.-F.;Ruan, S.-J. |
| 國立臺灣科技大學 |
2013 |
A practical NoC design for parallel des computation
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Yuan, R.;Ruan, S.-J.;Gotze, J. |
| 國立臺灣科技大學 |
2013 |
Hash-based linked-list histogram construction
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Peng, Y.-T.;Cheng, F.-C.;Ruan, S.-J.;Lin, C.-H. |
Showing items 51-60 of 115 (12 Page(s) Totally)
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