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Taiwan Academic Institutional Repository >
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"ruan shanq jang"
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| 國立臺灣大學 |
2003 |
Design and Analysis of Low Power Cache using Two-Level Filter Scheme
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Chang, Yen-Jen; Ruan, Shanq-Jang; Lai, Feipei |
| 國立臺灣大學 |
2002-10 |
Energy analysis of bipartition architecture for pipelined circuits
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Ruan, Shanq-Jang; Naroska, Edwin; Chang, Yen-Ren; Ho, Chia-Lin; Lai, Feipei |
| 國立臺灣大學 |
2002-09 |
Cache design for eliminating the address translation bottleneck and reducing the tag area cost
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Chang, Yen-Jen; Lai, Feipei; Ruan, Shanq-Jang |
| 國立臺灣大學 |
2002-09 |
Power analysis of bipartition and dual-encoding architecture for pipelined circuits
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Ruan, Shanq-Jang; Ho, Chia-Lin; Naroska, Edwin; Lai, Feipei |
| 國立臺灣大學 |
2002 |
ENPCO: An Entropy-Based Partition-Codec Algorithm to Reduce Power for bipartition-codec architecture in Pipelined Circuits
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Ruan, Shanq-Jang; Naroska, Edwin; Chang, Yen-Jen; Lai, Feipei; Schwiegelshohn, Uwe |
| 國立臺灣大學 |
2001-05 |
Synthesis of partition-codec architecture for low power and small area circuit design
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Ruan, Shanq-Jang; Lin, Jen-Chiun; Chen, Po-Hung; Tsai, Kun-Lin; Lai, Feipei |
| 國立臺灣大學 |
2001-05 |
An entropy-based algorithm to reduce area overhead for bipartition-codec architecture
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Chen, Po-Hung; Ruan, Shanq-Jang; Wu, Kuen-Pin; Hu, Dai-Xun; Lai, Feipei; Tsai, Kun-Lin |
| 國立臺灣大學 |
2001 |
Hierarchical Access Control Using the Secure Filter
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Wu, Kuen-Pin; Ruan, Shanq-Jang; Tseng, Chih-Kuang; Lai, Feipei |
| 國立臺灣大學 |
2001 |
A Bipartition-Codec Architecture to Reduce Power in Pipelined Circuits
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Ruan, Shanq-Jang; Shang, Rung-Ji; Lai, Feipei; Tsai, Kun-Lin |
| 國立臺灣大學 |
2000-12 |
An effective output-oriented algorithm for low power multipartition architecture
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Ruan, Shanq-Jang; Lin, Jen-Chiun; Chen, Po-Hung; Lai, Feipei; Tsai, Kun-Lin; Yu, Chung-Wei |
Showing items 11-20 of 22 (3 Page(s) Totally)
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