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Taiwan Academic Institutional Repository >
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"shanq jang ruan"
Showing items 1-10 of 31 (4 Page(s) Totally)
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| 臺大學術典藏 |
2018-09-10T07:43:14Z |
A Bipartition-Codec Architecture to Reduce Power in Pipelined Circuits
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Shanq-Jang Ruan,; Rung-Ji Shang,; Feipei Lai,; Shyh-Jong Chen,; FEI-PEI LAI; Xian-Jun Huang, |
| 臺大學術典藏 |
2018-09-10T06:03:24Z |
Low Power Scheduling Method using Multiple Supply Voltages
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Kun-Lin Tsai,; Ju-Yueh Lee,; Shanq-Jang Ruan,; Feipei Lai,; FEI-PEI LAI |
| 臺大學術典藏 |
2018-09-10T05:29:30Z |
Low Power Dynamic Bus Encoding for Deep Sub-micron Design
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Kun-Lin Tsai,; Shanq-Jang Ruan,; Li-Wei Chen,; Feipei Lai,; Edwin Naroska,; FEI-PEI LAI |
| 臺大學術典藏 |
2018-09-10T05:29:29Z |
A Low Power Scheduling Method Using Dual Vdd and Dual Vth
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Kun-Lin Tsai,; Szu-Wei Chang,; Feipei Lai,; Shanq-Jang Ruan,; FEI-PEI LAI |
| 臺大學術典藏 |
2018-09-10T04:59:56Z |
Circuit Partition and Reordering Technique for Low Power IP
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Kun-lin Tsai,; Shanq-jang Ruan,; Chun-ming Huang,; Edwin Naroska,; Feipei Lai,; FEI-PEI LAI |
| 臺大學術典藏 |
2018-09-10T04:36:06Z |
On Optimizing Power and Crosstalk for Bus Coupling Capacitance Using Genetic Algorithm
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Edwin Naroska,; Shanq-Jang Ruan,; Feipei Lai,; FEI-PEI LAI |
| 臺大學術典藏 |
2018-09-10T04:36:06Z |
State Reordering for Low Power Combinational Logic
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Kun-Lin Tsai,; Feipei Lai,; Shanq-Jang Ruan,; Szu-Wei Chang,; FEI-PEI LAI |
| 臺大學術典藏 |
2018-09-10T04:36:05Z |
A Novel Approach for Digital Waveform Compression
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Edwin Naroska,; Shanq-Jang Ruan,; Chia-Lin Ho,; Said Mchaalia,; Feipei Lai,; Uwe Schwiegelshohn,; FEI-PEI LAI |
| 臺大學術典藏 |
2018-09-10T04:15:43Z |
An Efficient Two-Level Filter Scheme for Low Power Cache
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Yen-Jen Chang; Feipei Lai; Shanq-Jang Ruan; FEI-PEI LAI |
| 臺大學術典藏 |
2018-09-10T04:15:42Z |
ENPCO: An Entropy-Based Partition-Codec Algorithm to Reduce Power for bipartition-codec architecture in Pipelined Circuits
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Shanq-Jang Ruan,; Edwin Naroska,; Yen-Ren Chang,; Feipei Lai,; Uwe Schwiegelshohn; FEI-PEI LAI |
Showing items 1-10 of 31 (4 Page(s) Totally)
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