|
"shen chiuan huei"的相關文件
顯示項目 1-6 / 6 (共1頁)
1
每頁顯示[10|25|50]項目
| 國立交通大學 |
2020-02-01 |
Effect of Seed Layer on Gate-All-Around Poly-Si Nanowire Negative-Capacitance FETs With MFMIS and MFIS Structures: Planar Capacitors to 3-D FETs
|
Chao, Tien-Sheng; Chen, Hsin-Yu; Huang, Yu-En; Chung, Chun-Chih; Shen, Chiuan-Huei; Kuo, Po-Yi; Lee, Shen-Yang; Chen, Han-Wei |
| 國立交通大學 |
2020-01-02T00:03:25Z |
Experimental Demonstration of Performance Enhancement of MFMIS and MFIS for 5-nm x 12.5-nm Poly-Si Nanowire Gate-All-Around Negative Capacitance FETs Featuring Seed-Layer and PMA-Free Process
|
Lee, Shen-Yang; Chen, Han-Wei; Shen, Chiuan-Huei; Kuo, Po-Yi; Chung, Chun-Chih; Huang, Yu-En; Chen, Hsin-Yu; Chao, Tien-Sheng |
| 國立交通大學 |
2019-12-13T01:12:24Z |
Experimental Demonstration of Stacked Gate- All-Around Poly-Si Nanowires Negative Capacitance FETs With Internal Gate Featuring Seed Layer and Free of Post-Metal Annealing Process
|
Lee, Shen-Yang; Chen, Han-Wei; Shen, Chiuan-Huei; Kuo, Po-Yi; Chung, Chun-Chih; Huang, Yu-En; Chen, Hsin-Yu; Chao, Tien-Sheng |
| 國立交通大學 |
2019-04-02T05:58:35Z |
Variable-Channel Junctionless Poly-Si FETs: Demonstration and Investigation With Different Body Doping Concentrations
|
Lin, Jer-Yi; Tsai, Chan-Yi; Shen, Chiuan-Huei; Chung, Chun-Chih; Kumar, Malkundi Puttaveerappa Vijay; Chao, Tien-Sheng |
| 國立交通大學 |
2018-08-21T05:53:29Z |
Stacked Sidewall-Damascene Double-Layer Poly-Si Trigate FETs With RTA-Improved Crystallinity
|
Shen, Chiuan-Huei; Kuo, Po-Yi; Chung, Chun-Chih; Lee, Sen-Yang; Chao, Tien-Sheng |
| 國立交通大學 |
2018-08-21T05:53:13Z |
Vertically Stacked Cantilever n-Type Poly-Si Junctionless Nanowire Transistor and Its Series Resistance Limit
|
Chung, Chris Chun-Chih; Shen, Chiuan-Huei; Lin, Jer-Yi; Chin, Chun-Chieh; Chao, Tien-Sheng |
顯示項目 1-6 / 6 (共1頁)
1
每頁顯示[10|25|50]項目
|
