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Taiwan Academic Institutional Repository >
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"shen iuan liu"
Showing items 1-25 of 264 (11 Page(s) Totally)
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| 臺大學術典藏 |
2021-09-21T23:19:37Z |
A Low-Jitter Sub-Sampling PLL with A Sub-Sampling DLL
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Qian, Yuan Cheng; Chao, Yen Yu; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:57Z |
A digital bang-bang phase-locked loop with automatic loop gain control and loop latency reduction
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Kuan, T.-K.;Liu, S.-I.; Kuan, T.-K.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:57Z |
A PVT-Tolerant MDLL Using a Frequency Calibrator and a Voltage Monitor.
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Chiu, Yu-Kai;Liu, Shen-Iuan; Chiu, Yu-Kai; Liu, Shen-Iuan; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:57Z |
Ultrasonic telemetry and neural stimulator with FSK-PWM signaling
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Luo, Y.-S.;Wang, J.-R.;Huang, W.-J.;Tsai, J.-Y.;Wu, I.-C.;Liao, Y.-F.;Tseng, W.-T.;Yen, C.-T.;Li, P.-C.;Liu, S.-I.; Luo, Y.-S.; Wang, J.-R.; Huang, W.-J.; Tsai, J.-Y.; Wu, I.-C.; Liao, Y.-F.; Tseng, W.-T.; Yen, C.-T.; Li, P.-C.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:57Z |
Ultrasonic wireless power and data communication for neural stimulation
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Tsai, J.-Y.;Huang, K.-H.;Wang, J.-R.;Liu, S.-I.;Li, P.-C.; Tsai, J.-Y.; Huang, K.-H.; Wang, J.-R.; Liu, S.-I.; Li, P.-C.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:56Z |
A 12-bit 3.4 MS/s two-step cyclic time-domain ADC in 0.18-μm CMOS
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Chen, L.-J.;Liu, S.-I.; Chen, L.-J.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:56Z |
An On-Chip Relaxation Oscillator with Comparator Delay Compensation
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Chang, Y.-A.;Adiono, T.;Hamidah, A.;Liu, S.-I.; Chang, Y.-A.; Adiono, T.; Hamidah, A.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:56Z |
A 13.4-MHz Relaxation Oscillator With Temperature Compensation
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Chang, Yi-An;Liu, Shen-Iuan; Chang, Yi-An; Liu, Shen-Iuan; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:56Z |
A PVT-Tolerant Injection-Locked Clock Multiplier with a Frequency Calibrator Using a Delay Time Detector
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Tien, C.-W.;Liu, S.-I.; Tien, C.-W.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:56Z |
A 2.4-GHz frequency-drift-compensated phase-locked loop with 2.43 ppm/°C temperature coefficient
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Hsieh, C.-E.;Liu, S.-I.; Hsieh, C.-E.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:55Z |
A Subharmonically Injection-Locked All-Digital PLL Without Main Divider
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Zeng, K.-H.;Kuan, T.-K.;Liu, S.-I.; Zeng, K.-H.; Kuan, T.-K.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:55Z |
A 10-bit 40-MS/s Time-Domain Two-Step ADC with Short Calibration Time
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Chen, L.-J.;Liu, S.-I.; Chen, L.-J.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:54Z |
A 20-MHz to 3-GHz wide-range multiphase delay-locked loop
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Chuang, C.-N.;Liu, S.-I.; Chuang, C.-N.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:54Z |
A 20-Gb/s transmitter with adaptive preemphasis in 65-nm CMOS technology
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Kao, S.-Y.;Liu, S.-I.; Kao, S.-Y.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:54Z |
A 132.6-GHz phase-locked loop in 65 nm digital CMOS
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Lin, B.-Y.;Liu, S.-I.; Lin, B.-Y.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:54Z |
A 3-25 Gb/s four-channel receiver with noise-canceling TIA and power-scalable sLA
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Chien, Y.-H.;Fu, K.-L.;Liu, S.-I.; Chien, Y.-H.; Fu, K.-L.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:53Z |
A 10-Gb/s Inductorless CMOS Analog Equalizer With an Interleaved Active Feedback Topology (vol 56, pg 97, 2009)
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Lu, Jian-Hao;Chen, Ke-Hou;Liu, Shen-Iuan; Lu, Jian-Hao; Chen, Ke-Hou; Liu, Shen-Iuan; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:53Z |
A leakage-compensated PLL in 65-nm CMOS technology
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Hung, C.-C.;Liu, S.-I.; Hung, C.-C.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:52Z |
A 10-20 Gb/s CDR circuit with 6200ppm frequency tracking
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Huang, C.-C.;Tseng, K.-W.;Liu, S.-I.; Huang, C.-C.; Tseng, K.-W.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:52Z |
A 2.25-2.7 GHz Area-Efficient Subharmonically Injection-Locked Fractional-N Frequency Synthesizer with a Fast-Converging Correlation Loop
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Tseng, Y.-H.;Yeh, C.-W.;Liu, S.-I.; Tseng, Y.-H.; Yeh, C.-W.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:52Z |
A 5 Gb/s Voltage-Mode Transmitter Using Adaptive Time-Based De-Emphasis
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Su, W.-J.;Liu, S.-I.; Su, W.-J.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:51Z |
A Bang-Bang Phase-Locked Loop Using Automatic Loop Gain Control and Loop Latency Reduction Techniques
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Kuan, T.-K.;Liu, S.-I.; Kuan, T.-K.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:51Z |
A 6.7 MHz to 1.24 GHz 0.0318 mm 2 Fast-Locking All-Digital DLL Using Phase-Tracing Delay Unit in 90 nm CMOS
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Hsieh, M.-H.; Chen, L.-H.; Liu, S.-I.; Chen, C.C.-P.; SHEN-IUAN LIU; Hsieh, M.-H.;Chen, L.-H.;Liu, S.-I.;Chen, C.C.-P. |
| 臺大學術典藏 |
2020-06-11T06:34:51Z |
A Voltage Multiplier With Adaptive Threshold Voltage Compensation
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Luo, Y.-S.;Liu, S.-I.; Luo, Y.-S.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:50Z |
A 33.6-to-33.8 Gb/s burst-mode CDR in 90 nm CMOS technology
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Cho, L.-C.;Lee, C.;Hung, C.-C.;Liu, S.-I.; Cho, L.-C.; Lee, C.; Hung, C.-C.; Liu, S.-I.; SHEN-IUAN LIU |
Showing items 1-25 of 264 (11 Page(s) Totally)
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