臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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Showing items 101-110 of 264 (27 Page(s) Totally)
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Institution	Date	Title	Author
臺大學術典藏	2018-09-10T08:18:16Z	An integrating analog-to-digital data converter with variable resolution	I-Hsin Wang;Shen-Iuan Liu; I-Hsin Wang; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T08:18:16Z	A 1.25GHz fast-locked all-digital phase-locked loop with supply noise suppression	Chao-Ching Hung;I-Fong Chen;Shen-Iuan Liu; Chao-Ching Hung; I-Fong Chen; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T08:18:15Z	A merged CMOS digital near-end crosstalk canceller and analog equalizer for multi-lane serial-link receivers	Jian-Hao Lu;Shen-Iuan Liu; Jian-Hao Lu; Shen-Iuan Liu; SHEN-IUAN LIU; Liu, Shen-Iuan
臺大學術典藏	2018-09-10T07:42:02Z	類比排序與中值電路	�B�`�W; ��\|��; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:42:02Z	信號處理裝置	陳伯奇; 劉深淵; 曹恆偉; 吳靜雄; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:42:02Z	Divide by 4/5 counter	楊清淵; 劉深淵; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:42:02Z	除4/5電路	��M�W; �B�`�W; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:42:02Z	Direct Digital Frequency Synthesizer	游宗榜; 劉深淵; 曹恆偉; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:42:01Z	A 40Gb/s decision feedback equalizer using back-gate feedback technique	Chang-Lin Hsieh;Shen-Iuan Liu; Chang-Lin Hsieh; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:42:01Z	A 10Gb/s inductorless quarter-rate clock and data recovery circuit in 0.13um CMOS	Hong-Lin Chu, Chang-Lin Hsieh;Shen-Iuan Liu; Hong-Lin Chu, Chang-Lin Hsieh; Shen-Iuan Liu; SHEN-IUAN LIU

Showing items 101-110 of 264 (27 Page(s) Totally)
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