臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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机构	日期	题名	作者
臺大學術典藏	2018-09-10T07:42:02Z	Divide by 4/5 counter	楊清淵; 劉深淵; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:42:02Z	除4/5電路	��M�W; �B�`�W; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:42:02Z	Direct Digital Frequency Synthesizer	游宗榜; 劉深淵; 曹恆偉; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:42:01Z	A 40Gb/s decision feedback equalizer using back-gate feedback technique	Chang-Lin Hsieh;Shen-Iuan Liu; Chang-Lin Hsieh; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:42:01Z	A 10Gb/s inductorless quarter-rate clock and data recovery circuit in 0.13um CMOS	Hong-Lin Chu, Chang-Lin Hsieh;Shen-Iuan Liu; Hong-Lin Chu, Chang-Lin Hsieh; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:42:01Z	A CBSC second-order sigma-delta modulator in 3μm LTPS-TFT technology	Wei-Ming Lin;Chan-Fei Lin;Shen-Iuan Liu; Wei-Ming Lin; Chan-Fei Lin; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:42:01Z	A delay-locked loop with digital background calibration	Wei-Ming Lin;Kuang-Fu Teng;Shen-Iuan Liu; Wei-Ming Lin; Kuang-Fu Teng; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:42:01Z	Loop latency reduction technique for all-digital clock and data recovery circuits	I-Fong Chen;Rong-Jyi Yang;Shen-Iuan Liu; I-Fong Chen; Rong-Jyi Yang; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:42:00Z	A 43.7mW 96GHz phase-locked loop in 65nm CMOS technology	Kun-Hung Tsai;Shen-Iuan Liu; Kun-Hung Tsai; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:42:00Z	A wireless power telemetry with self-calibrated resonant frequency	SHEN-IUAN LIU; Shen-Iuan Liu; Wei-Jen Huang;Chein-Lung Chen;Shen-Iuan Liu; Wei-Jen Huang; Chein-Lung Chen
臺大學術典藏	2018-09-10T07:42:00Z	A frequency synthesizer for mode-1 MB-OFDM UWB applications	Jung-Yu Chang;Che-Wei Fan;Shen-Iuan Liu; Jung-Yu Chang; Che-Wei Fan; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:42:00Z	An all-digital clock generator for dynamic frequency scaling	Wei-Ming Lin;Chao-Chyun Chen;Shen-Iuan Liu; Wei-Ming Lin; Chao-Chyun Chen; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:42:00Z	A 140MS/s 10-bit Pipelined ADC with a Folded S/H Stage	Hwei-Yu Lee;Shen-Iuan Liu; Hwei-Yu Lee; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:42:00Z	A 132.7-to-143.5GHz injection-locked frequency divider in 65nm CMOS	Bo-Yu Lin;Shen-Iuan Liu; Bo-Yu Lin; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:41:59Z	High Speed CMOS Interface Circuits for IEEE-1394 High Performance Serial Bus	Guang-Kaai Dehng; Jong-Woei Chen; Wei-Hung Chen; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:41:59Z	A leakage-suppression technique for phase-locked systems in 65nm CMOS	Chao-Ching Hung;Shen-Iuan Li; Chao-Ching Hung; Shen-Iuan Li; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:41:59Z	A 128.24-to-137.00GHz injection-locked frequency divider in 65nm CMOS	Bo-Yu Lin;Kun-Hung Tsai;Shen-Iuan Liu; Bo-Yu Lin; Kun-Hung Tsai; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:41:58Z	A 1.5GHz all-digital spread spectrum clock generator	Sheng-You Lin;Shen-Iuan Liu; Sheng-You Lin; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:41:58Z	A 1.5GHz phase-locked loop with leakage current suppression in 65nm CMOS	Jung-Yu Chang;Shen-Iuan Liu; Jung-Yu Chang; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:41:57Z	A 10Gb/s inductorless CMOS analog equalizer with interleaved active feedback topology	Jian-Hao Lu;Ke-Hou Chen;Shen-Iuan Liu; Jian-Hao Lu; Ke-Hou Chen; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:41:57Z	A 33.6-to-33.8Gb/s burst-mode CDR in 90nm CMOS technology	Lan-Chou Cho;Chihun Lee;Chao-Ching Hung;Shen-Iuan Liu; Lan-Chou Cho; Chihun Lee; Chao-Ching Hung; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:41:57Z	A fully-differential comparator-based switched-capacitor delta-sigma modulator	Mu-Chen Huang;Shen-Iuan Liu; Mu-Chen Huang; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:41:56Z	Low-power clock-deskew buffer for high-speed digital circuits	Shen-Iuan Liu; Jiunn-Hwa Lee; Hen-Wai Tsao; HEN-WAI TSAO; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:41:56Z	Low-voltage BiCMOS four-quadrant multiplier and squarer	Shen-Iuan Liu; Jiin-Long Lee; Cheng-Chieh Chang; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:41:56Z	Low-voltage BiCMOS four-quadrant multiplier using triode-region transistors	Shen-Iuan Liu; Jiin-Long Lee; Cheng-Chieh Chang; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:41:56Z	Dual-input RC integrator and differentiator with tuneable time constants using current feedback amplifiers	Lee, Jiin-Long; Liu, Shen-Iuan; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:41:56Z	A phase-locked loop with self-calibrated charge pumps in 3µm LTPS-TFT Technology	Wei-Ming Lin; Shen-Iuan Liu; Chun-Hung Kuo; Chun-Huai Li; Yao-Jen Hsieh; Chun-Ting Liu; SHEN-IUAN LIU; Wei-Ming Lin;Shen-Iuan Liu;Chun-Hung Kuo;Chun-Huai Li;Yao-Jen Hsieh;Chun-Ting Liu
臺大學術典藏	2018-09-10T07:41:56Z	A single-PLL UWB frequency synthesizer using multiphase coupled ring oscillator and current-reused multiplier	Jung-Yu Chang;Che-Wei Fan;Che-Fu Liang;Shen-Iuan Liu; Jung-Yu Chang; Che-Wei Fan; Che-Fu Liang; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:41:55Z	Analogue BiCMOS squarer and its applications	Cheng-Chieh Chang; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:41:55Z	Spice Macro model for MAGFET and its applications	Shen-Iuan Liu; Jian-Fan Wei; Guo-Ming Sung,; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:08:37Z	20Gb/s 1/4-rate and 40Gb/s 1/8-rate burst-mode CDR circuits in 0.13μm CMOS	Hong-Lin Chu;Chaung-Lin Hsieh;Shen-Iuan Liu; Hong-Lin Chu; Chaung-Lin Hsieh; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:08:37Z	A 57.1-59GHz CMOS fractional-N frequency synthesizer using quantization noise shifting technique	Chao-Ching Hung;Chihun Lee;Lan-Chou Cho;Shen-Iuan Liu; Chao-Ching Hung; Chihun Lee; Lan-Chou Cho; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:08:37Z	A 15-20GHz delay-locked loop in 90nm CMOS technology	Jung-Yu Chang;Chi-Nan Chuang;Shen-Iuan Liu; Jung-Yu Chang; Chi-Nan Chuang; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:08:37Z	A 4-bit 10GSample/sec flash ADC with merged interpolation and reference voltage	I-Hsin Wang;Shen-Iuan Liu; I-Hsin Wang; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:08:37Z	直接數位頻率合成器	游宗榜; 劉深淵; 曹恆偉; SHEN-IUAN LIU; 游宗榜; 劉深淵; 曹恆偉
臺大學術典藏	2018-09-10T07:08:36Z	93.5~ 109.4GHz CMOS injection-locked frequency divider with 15.3% locking range	Lan-Chou Cho;Kun-Hung Tsai;Chao-Ching Hung;Shen-Iuan Liu; Lan-Chou Cho; Kun-Hung Tsai; Chao-Ching Hung; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:08:36Z	A merged CMOS digital near-end crosstalk canceller and analog equalizer for multi-lane serial-link receivers	Jian-Hao Lu; Ke-Hou Chen; An-Ming Lee; Ting-Ying Wu; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:08:36Z	A dual-band 61.4~63GHz/ 75.5~77.5GHz CMOS receiver in a 90nm technology	Ke-Hou Chen; Chihun Lee; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:08:36Z	A sub-1V low-dropout regulator with an on-chip voltage reference	Wei-Jen Huang; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:08:35Z	A digitally calibrated 64.3-66.2GHz phase-locked loop	Kun-Hung Tsai; Jia-Hao Wu; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:08:35Z	Frequency dividers with enhanced locking range	Kun-Hung Tsai; Jia-Hao Wu; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:08:34Z	A 3~8GHz delay-locked loop with cycle jitter calibration	Chi-Nan Chuang;Shen-Iuan Liu; Chi-Nan Chuang; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:08:34Z	An infinite phase shift delay-locked loop with voltage-controlled sawtooth delay line	Chao-Chyun Chen;Shen-Iuan Liu; Chao-Chyun Chen; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:08:34Z	A 40-Gb/s CMOS serial-link receiver with adaptive equalization and clock/data recovery	Chih-Fan Liao;Shen-Iuan Liu; Chih-Fan Liao; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:08:34Z	Full-Rate Bang-Bang Phase/Frequency Detectors for Unilateral Continuous-Rate CDRs	SHEN-IUAN LIU; Liu, Shen-Iuan; Lin, Shao-Hung; Lin, Shao-Hung;Liu, Shen-Iuan
臺大學術典藏	2018-09-10T07:08:33Z	A jitter-tolerance-enhanced CDR using a GDCO-based phase detector	Che-Fu Liang;Sy-Chyuan Hwu;Shen-Iuan Liu; Che-Fu Liang; Sy-Chyuan Hwu; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:08:33Z	Capacitor-free low dropout regulators using nested Miller compensation with active resistor and 1-bit programmable capacitor array	Wei-Jen Huang; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:08:33Z	A delay-locked loop with statistical background calibration	Shao-Ku Kao;Shen-Iuan Liu; Shao-Ku Kao; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:08:33Z	10Gbps inductorless CDRs with digital frequency calibration	Che-Fu Liang;Hong-Lin Chu;Shen-Iuan Liu; Che-Fu Liang; Hong-Lin Chu; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:08:32Z	An all-digital fast-locking programmable DLL-based clock generator	Chuan-Kang Liang; Rong-Jyi Yang; Shen-Iuan Liu; SHEN-IUAN LIU

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