臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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显示项目 131-155 / 264 (共11页)
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机构	日期	题名	作者
臺大學術典藏	2018-09-10T07:41:56Z	Dual-input RC integrator and differentiator with tuneable time constants using current feedback amplifiers	Lee, Jiin-Long; Liu, Shen-Iuan; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:41:56Z	A phase-locked loop with self-calibrated charge pumps in 3µm LTPS-TFT Technology	Wei-Ming Lin; Shen-Iuan Liu; Chun-Hung Kuo; Chun-Huai Li; Yao-Jen Hsieh; Chun-Ting Liu; SHEN-IUAN LIU; Wei-Ming Lin;Shen-Iuan Liu;Chun-Hung Kuo;Chun-Huai Li;Yao-Jen Hsieh;Chun-Ting Liu
臺大學術典藏	2018-09-10T07:41:56Z	A single-PLL UWB frequency synthesizer using multiphase coupled ring oscillator and current-reused multiplier	Jung-Yu Chang;Che-Wei Fan;Che-Fu Liang;Shen-Iuan Liu; Jung-Yu Chang; Che-Wei Fan; Che-Fu Liang; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:41:55Z	Analogue BiCMOS squarer and its applications	Cheng-Chieh Chang; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:41:55Z	Spice Macro model for MAGFET and its applications	Shen-Iuan Liu; Jian-Fan Wei; Guo-Ming Sung,; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:08:37Z	20Gb/s 1/4-rate and 40Gb/s 1/8-rate burst-mode CDR circuits in 0.13μm CMOS	Hong-Lin Chu;Chaung-Lin Hsieh;Shen-Iuan Liu; Hong-Lin Chu; Chaung-Lin Hsieh; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:08:37Z	A 57.1-59GHz CMOS fractional-N frequency synthesizer using quantization noise shifting technique	Chao-Ching Hung;Chihun Lee;Lan-Chou Cho;Shen-Iuan Liu; Chao-Ching Hung; Chihun Lee; Lan-Chou Cho; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:08:37Z	A 15-20GHz delay-locked loop in 90nm CMOS technology	Jung-Yu Chang;Chi-Nan Chuang;Shen-Iuan Liu; Jung-Yu Chang; Chi-Nan Chuang; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:08:37Z	A 4-bit 10GSample/sec flash ADC with merged interpolation and reference voltage	I-Hsin Wang;Shen-Iuan Liu; I-Hsin Wang; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:08:37Z	直接數位頻率合成器	游宗榜; 劉深淵; 曹恆偉; SHEN-IUAN LIU; 游宗榜; 劉深淵; 曹恆偉
臺大學術典藏	2018-09-10T07:08:36Z	93.5~ 109.4GHz CMOS injection-locked frequency divider with 15.3% locking range	Lan-Chou Cho;Kun-Hung Tsai;Chao-Ching Hung;Shen-Iuan Liu; Lan-Chou Cho; Kun-Hung Tsai; Chao-Ching Hung; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:08:36Z	A merged CMOS digital near-end crosstalk canceller and analog equalizer for multi-lane serial-link receivers	Jian-Hao Lu; Ke-Hou Chen; An-Ming Lee; Ting-Ying Wu; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:08:36Z	A dual-band 61.4~63GHz/ 75.5~77.5GHz CMOS receiver in a 90nm technology	Ke-Hou Chen; Chihun Lee; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:08:36Z	A sub-1V low-dropout regulator with an on-chip voltage reference	Wei-Jen Huang; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:08:35Z	A digitally calibrated 64.3-66.2GHz phase-locked loop	Kun-Hung Tsai; Jia-Hao Wu; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:08:35Z	Frequency dividers with enhanced locking range	Kun-Hung Tsai; Jia-Hao Wu; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:08:34Z	A 3~8GHz delay-locked loop with cycle jitter calibration	Chi-Nan Chuang;Shen-Iuan Liu; Chi-Nan Chuang; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:08:34Z	An infinite phase shift delay-locked loop with voltage-controlled sawtooth delay line	Chao-Chyun Chen;Shen-Iuan Liu; Chao-Chyun Chen; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:08:34Z	A 40-Gb/s CMOS serial-link receiver with adaptive equalization and clock/data recovery	Chih-Fan Liao;Shen-Iuan Liu; Chih-Fan Liao; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:08:34Z	Full-Rate Bang-Bang Phase/Frequency Detectors for Unilateral Continuous-Rate CDRs	SHEN-IUAN LIU; Liu, Shen-Iuan; Lin, Shao-Hung; Lin, Shao-Hung;Liu, Shen-Iuan
臺大學術典藏	2018-09-10T07:08:33Z	A jitter-tolerance-enhanced CDR using a GDCO-based phase detector	Che-Fu Liang;Sy-Chyuan Hwu;Shen-Iuan Liu; Che-Fu Liang; Sy-Chyuan Hwu; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:08:33Z	Capacitor-free low dropout regulators using nested Miller compensation with active resistor and 1-bit programmable capacitor array	Wei-Jen Huang; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:08:33Z	A delay-locked loop with statistical background calibration	Shao-Ku Kao;Shen-Iuan Liu; Shao-Ku Kao; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:08:33Z	10Gbps inductorless CDRs with digital frequency calibration	Che-Fu Liang;Hong-Lin Chu;Shen-Iuan Liu; Che-Fu Liang; Hong-Lin Chu; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:08:32Z	An all-digital fast-locking programmable DLL-based clock generator	Chuan-Kang Liang; Rong-Jyi Yang; Shen-Iuan Liu; SHEN-IUAN LIU

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