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機構	日期	題名	作者
臺大學術典藏	2018-09-10T07:08:35Z	Frequency dividers with enhanced locking range	Kun-Hung Tsai; Jia-Hao Wu; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:08:34Z	A 3~8GHz delay-locked loop with cycle jitter calibration	Chi-Nan Chuang;Shen-Iuan Liu; Chi-Nan Chuang; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:08:34Z	An infinite phase shift delay-locked loop with voltage-controlled sawtooth delay line	Chao-Chyun Chen;Shen-Iuan Liu; Chao-Chyun Chen; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:08:34Z	A 40-Gb/s CMOS serial-link receiver with adaptive equalization and clock/data recovery	Chih-Fan Liao;Shen-Iuan Liu; Chih-Fan Liao; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:08:34Z	Full-Rate Bang-Bang Phase/Frequency Detectors for Unilateral Continuous-Rate CDRs	SHEN-IUAN LIU; Liu, Shen-Iuan; Lin, Shao-Hung; Lin, Shao-Hung;Liu, Shen-Iuan
臺大學術典藏	2018-09-10T07:08:33Z	A jitter-tolerance-enhanced CDR using a GDCO-based phase detector	Che-Fu Liang;Sy-Chyuan Hwu;Shen-Iuan Liu; Che-Fu Liang; Sy-Chyuan Hwu; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:08:33Z	Capacitor-free low dropout regulators using nested Miller compensation with active resistor and 1-bit programmable capacitor array	Wei-Jen Huang; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:08:33Z	A delay-locked loop with statistical background calibration	Shao-Ku Kao;Shen-Iuan Liu; Shao-Ku Kao; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:08:33Z	10Gbps inductorless CDRs with digital frequency calibration	Che-Fu Liang;Hong-Lin Chu;Shen-Iuan Liu; Che-Fu Liang; Hong-Lin Chu; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:08:32Z	An all-digital fast-locking programmable DLL-based clock generator	Chuan-Kang Liang; Rong-Jyi Yang; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:08:32Z	A digital calibration technique for charge pumps in phase-locked systems	Che-Fu Liang;Shin-Hua Chen;Shen-Iuan Liu; Che-Fu Liang; Shin-Hua Chen; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T06:35:23Z	A wide-range all-digital duty cycle corrector with a period monitor	Shao-Ku Kao; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T06:35:23Z	A fast-locked all-digital delay-locked loop with non-50% input duty cycle	Shao-Ku Kao; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T06:35:23Z	Four-Quadrant Three-Input Multiplier	劉深淵; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T06:35:22Z	An infinite phase shift delay-locked loop with voltage-controlled sawtooth delay line	Chao-Chyun Chen; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T06:35:22Z	An all-digital reused-SAR delay-locked loop with adjustable duty cycle	Wei-Ming Lin; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T06:35:22Z	A half-rate bang-bang phase/frequency detector for continuous-rate CDR circuits	Shao-Hung Lin; Chang-Lin Hsieh; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T06:35:21Z	A jitter-tolerance-enhanced CDR using a GDCO-based phase detector	Che-Fu Liang; Sy-Chyuan Hwu; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T06:35:19Z	Spur-suppression techniques for frequency synthesizers	Che-Fu Liang; Hsin-Hua Chen; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T06:35:19Z	A low-jitter spread spectrum clock generator using FDMP	Ding-Shiuan Shen; Shen-Iuan Liu; Ding-Shiuan Shen; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T06:35:19Z	A DLL-based variable-phase clock buffer	Chao-Chyun Chen; Jung-Yu Chang; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T06:35:18Z	A multi-band burst-mode clock and data recovery circuit	Che-Fu Liang; Sy-Chyuan Hwu; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T06:35:17Z	A time-constant calibrated phase-locked loop with a fast-locked time	Sung-Rung Han; Chi-Nan Chuang; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T06:35:17Z	An ultra-wideband 0.4-10GHz LNA in 0.18um CMOS	Bo-Jiun Chen; Shen-Iuan Liu; SHEN-IUAN LIU; Jian-Hao Lu; Ke-Hou Chen
臺大學術典藏	2018-09-10T06:02:36Z	利用偏壓回受技術之金氧半四象限乘法	劉深淵; 吳靜雄; SHEN-IUAN LIU

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