臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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Showing items 151-160 of 264 (27 Page(s) Totally)
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Institution	Date	Title	Author
臺大學術典藏	2018-09-10T07:08:33Z	A jitter-tolerance-enhanced CDR using a GDCO-based phase detector	Che-Fu Liang;Sy-Chyuan Hwu;Shen-Iuan Liu; Che-Fu Liang; Sy-Chyuan Hwu; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:08:33Z	Capacitor-free low dropout regulators using nested Miller compensation with active resistor and 1-bit programmable capacitor array	Wei-Jen Huang; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:08:33Z	A delay-locked loop with statistical background calibration	Shao-Ku Kao;Shen-Iuan Liu; Shao-Ku Kao; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:08:33Z	10Gbps inductorless CDRs with digital frequency calibration	Che-Fu Liang;Hong-Lin Chu;Shen-Iuan Liu; Che-Fu Liang; Hong-Lin Chu; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:08:32Z	An all-digital fast-locking programmable DLL-based clock generator	Chuan-Kang Liang; Rong-Jyi Yang; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:08:32Z	A digital calibration technique for charge pumps in phase-locked systems	Che-Fu Liang;Shin-Hua Chen;Shen-Iuan Liu; Che-Fu Liang; Shin-Hua Chen; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T06:35:23Z	A wide-range all-digital duty cycle corrector with a period monitor	Shao-Ku Kao; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T06:35:23Z	A fast-locked all-digital delay-locked loop with non-50% input duty cycle	Shao-Ku Kao; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T06:35:23Z	Four-Quadrant Three-Input Multiplier	劉深淵; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T06:35:22Z	An infinite phase shift delay-locked loop with voltage-controlled sawtooth delay line	Chao-Chyun Chen; Shen-Iuan Liu; SHEN-IUAN LIU

Showing items 151-160 of 264 (27 Page(s) Totally)
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