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Showing items 151-175 of 264 (11 Page(s) Totally)
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Institution	Date	Title	Author
臺大學術典藏	2018-09-10T07:08:33Z	A jitter-tolerance-enhanced CDR using a GDCO-based phase detector	Che-Fu Liang;Sy-Chyuan Hwu;Shen-Iuan Liu; Che-Fu Liang; Sy-Chyuan Hwu; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:08:33Z	Capacitor-free low dropout regulators using nested Miller compensation with active resistor and 1-bit programmable capacitor array	Wei-Jen Huang; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:08:33Z	A delay-locked loop with statistical background calibration	Shao-Ku Kao;Shen-Iuan Liu; Shao-Ku Kao; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:08:33Z	10Gbps inductorless CDRs with digital frequency calibration	Che-Fu Liang;Hong-Lin Chu;Shen-Iuan Liu; Che-Fu Liang; Hong-Lin Chu; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:08:32Z	An all-digital fast-locking programmable DLL-based clock generator	Chuan-Kang Liang; Rong-Jyi Yang; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:08:32Z	A digital calibration technique for charge pumps in phase-locked systems	Che-Fu Liang;Shin-Hua Chen;Shen-Iuan Liu; Che-Fu Liang; Shin-Hua Chen; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T06:35:23Z	A wide-range all-digital duty cycle corrector with a period monitor	Shao-Ku Kao; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T06:35:23Z	A fast-locked all-digital delay-locked loop with non-50% input duty cycle	Shao-Ku Kao; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T06:35:23Z	Four-Quadrant Three-Input Multiplier	劉深淵; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T06:35:22Z	An infinite phase shift delay-locked loop with voltage-controlled sawtooth delay line	Chao-Chyun Chen; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T06:35:22Z	An all-digital reused-SAR delay-locked loop with adjustable duty cycle	Wei-Ming Lin; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T06:35:22Z	A half-rate bang-bang phase/frequency detector for continuous-rate CDR circuits	Shao-Hung Lin; Chang-Lin Hsieh; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T06:35:21Z	A jitter-tolerance-enhanced CDR using a GDCO-based phase detector	Che-Fu Liang; Sy-Chyuan Hwu; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T06:35:19Z	Spur-suppression techniques for frequency synthesizers	Che-Fu Liang; Hsin-Hua Chen; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T06:35:19Z	A low-jitter spread spectrum clock generator using FDMP	Ding-Shiuan Shen; Shen-Iuan Liu; Ding-Shiuan Shen; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T06:35:19Z	A DLL-based variable-phase clock buffer	Chao-Chyun Chen; Jung-Yu Chang; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T06:35:18Z	A multi-band burst-mode clock and data recovery circuit	Che-Fu Liang; Sy-Chyuan Hwu; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T06:35:17Z	A time-constant calibrated phase-locked loop with a fast-locked time	Sung-Rung Han; Chi-Nan Chuang; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T06:35:17Z	An ultra-wideband 0.4-10GHz LNA in 0.18um CMOS	Bo-Jiun Chen; Shen-Iuan Liu; SHEN-IUAN LIU; Jian-Hao Lu; Ke-Hou Chen
臺大學術典藏	2018-09-10T06:02:36Z	利用偏壓回受技術之金氧半四象限乘法	劉深淵; 吳靜雄; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T06:02:36Z	Differential-difference current conveyor applications	劉深淵; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T06:02:36Z	向量和裝置	劉深淵; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T06:02:36Z	Vector Summation Device	劉深淵; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T06:02:36Z	互補式金氧半雙差動電流運輸器及其應用之積分電路和濾波電路	劉深淵; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T06:02:36Z	利用金氧半電晶體於飽和區之平方律特性之金氧半四象限乘法器與平方器	劉深淵; 吳靜雄; 黃育賢; SHEN-IUAN LIU

Showing items 151-175 of 264 (11 Page(s) Totally)
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