| 臺大學術典藏 |
2020-06-11T06:34:50Z |
A 1.5 GHz all-digital spread-spectrum clock generator
|
Lin, S.-Y.;Liu, S.-I.; Lin, S.-Y.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:49Z |
A 13.56 MHz 88.7%-PCE Voltage Doubling Rectifier Using Adaptive Delay Time and Pulse-Width Control
|
Luo, Y.-S.;Lin, H.-H.;Liu, S.-I.; Luo, Y.-S.; Lin, H.-H.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:49Z |
A divider-less sub-harmonically injection-locked PLL with self-adjusted injection timing
|
Lee, I.-T.;Chen, Y.-J.;Liu, S.-I.;Jou, C.-P.;Hsueh, F.-L.;Hsieh, H.-H.; Lee, I.-T.; Chen, Y.-J.; Liu, S.-I.; Jou, C.-P.; Hsueh, F.-L.; Hsieh, H.-H.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:49Z |
A silicon nanowire-based bio-sensing system with digitized outputs for acute myocardial infraction diagnosis
|
Shen, S.-H.;Ting, C.-Y.;Liu, C.-Y.;Cheng, H.;Liu, S.-I.;Lin, C.-T.; Shen, S.-H.; Ting, C.-Y.; Liu, C.-Y.; Cheng, H.; Liu, S.-I.; Lin, C.-T.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:48Z |
A 2×25 Gb/s clock and data recovery with background amplitude-locked loop
|
Kao, C.-K.;Fu, K.-L.;Liu, S.-I.; Kao, C.-K.; Fu, K.-L.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:48Z |
A digital bang-bang phase-locked loop with bandwidth calibration
|
Chiang, C.-H.;Huang, C.-C.;Liu, S.-I.; Chiang, C.-H.; Huang, C.-C.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:48Z |
A 5-20 Gb/s power scalable adaptive linear equalizer using edge counting
|
Lin, Y.-F.;Huang, C.-C.;Lee, J.-Y.M.;Chang, C.-T.;Liu, S.-I.; Lin, Y.-F.; Huang, C.-C.; Lee, J.-Y.M.; Chang, C.-T.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:48Z |
A 0.3V 10bit 7.3fJ/conversion-step SAR ADC in 0.18μm CMOS
|
Hsieh, C.-E.;Liu, S.-I.; Hsieh, C.-E.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:48Z |
A digital MDLL using switched biasing technique to reduce low-frequency phase noise
|
Chiang, C.-H.;Huang, C.-C.;Kuan, T.-K.;Liu, S.-I.; Chiang, C.-H.; Huang, C.-C.; Kuan, T.-K.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:47Z |
A low-input-swing AC-DC voltage multiplier using Schottky diodes
|
Luo, Y.-S.;Liu, S.-I.; Luo, Y.-S.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:47Z |
A 0.43pJ/bit true random number generator
|
Kuan, T.-K.;Chiang, Y.-H.;Liu, S.-I.; Kuan, T.-K.; Chiang, Y.-H.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:45Z |
CMOS Squarer and Four-Quadrant Multiplier
|
Liu, S.-I.;Hwang, Y.-S.; Liu, S.-I.; Hwang, Y.-S.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:45Z |
New Current Mode Biquad Filters Using Current Followers
|
Liu, S.-I.;Chen, J.-J.;Hwang, Y.-S.; Liu, S.-I.; Chen, J.-J.; Hwang, Y.-S.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:44Z |
New Current-Feedback Amplifier-Based Universal Biquadratic Filter
|
Liu, S.-I.;Wu, D.-S.; Liu, S.-I.; Wu, D.-S.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:44Z |
CMOS Analog Divider and Four-Quadrant Multiplier Using Pool Circuits
|
Liu, S.-I.;Chang, C.-C.; Liu, S.-I.; Chang, C.-C.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:44Z |
Dual-Input Differentiators and Integrators with Tunable Time Constants Using Current Conveyors
|
Liu, S.-I.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:42Z |
Linear transformation all-pole filters based on current conveyors
|
Hwang, Y.-S.;Liu, S.-I.;Wu, D.-S.;Wu, Y.-P.; Hwang, Y.-S.; Liu, S.-I.; Wu, D.-S.; Wu, Y.-P.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:42Z |
CMOS four-quadrant multiplier using active attenuators
|
Llu, S.-I.;Chang, C.-C.; Llu, S.-I.; Chang, C.-C.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:41Z |
Sinusoidal oscillators with single element control using a current-feedback amplifier
|
Liu, S.-I.;Shih, C.-S.;Wu, D.-S.; Liu, S.-I.; Shih, C.-S.; Wu, D.-S.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:41Z |
CMOS subthreshold four-quadrant multiplier based on unbalanced source-coupled pairs
|
Liu, S.-I.;Chang, C.-C.; Liu, S.-I.; Chang, C.-C.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:41Z |
Multiphase sinusoidal oscillator using second-generation current conveyors
|
Wu, D.-S.;Liu, S.-I.;Hwang, Y.-S.;Wu, Y.-P.; Wu, D.-S.; Liu, S.-I.; Hwang, Y.-S.; Wu, Y.-P.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:40Z |
Electrically-programmable MOSFET-C filter
|
Liu, S.I.;Tsao, H.W.;Wu, J.; Liu, S.I.; Tsao, H.W.; Wu, J.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:39Z |
Microwave resonant absorption of viruses through dipolar coupling with confined acoustic vibrations
|
Liu, T.-M.;Chen, H.-P.;Wang, L.-T.;Wang, J.-R.;Luo, T.-N.;Chen, Y.-J.;Liu, S.-I.;Sun, C.-K.; Liu, T.-M.; Chen, H.-P.; Wang, L.-T.; Wang, J.-R.; Luo, T.-N.; Chen, Y.-J.; Liu, S.-I.; Sun, C.-K.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:39Z |
Universal filter using two current-feedback amplifiers
|
Liu, S.-I.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:38Z |
CCII-based fuzzy membership function and max/min circuits
|
Liu, S.-I.;Hwang, Y.-S.;Tsay, J.-H.; Liu, S.-I.; Hwang, Y.-S.; Tsay, J.-H.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:38Z |
CMOS four-quadrant multiplier using bias offset crosscoupled pairs
|
Liu, S.-I.;Hwang, Y.-S.; Liu, S.-I.; Hwang, Y.-S.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:38Z |
Realisation of R-L and C-D impedances using a current feedback amplifier and its applications
|
Liu, S.-I.;Hwang, Y.-S.; Liu, S.-I.; Hwang, Y.-S.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:37Z |
258.16-259.95GHz injection-locked frequency divider
|
Lee, I.-T.;Wang, C.-H.;Lin, B.-Y.;Liu, S.-I.; Lee, I.-T.; Wang, C.-H.; Lin, B.-Y.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:37Z |
Design of a CMOS low-power and low-voltage four-quadrant analog multiplier
|
Liu, W.;Liu, S.-I.; Liu, W.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:36Z |
2011 Proceedings of Technical Papers: IEEE Asian Solid-State Circuits Conference 2011, A-SSCC 2011: Foreword
|
Liu, S.-I.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2018-09-10T15:26:01Z |
A subharmonically injection-locked PLL with calibrated injection pulsewidth
|
Chih-Lu Wei;Ting-Kuei Kuan;Shen-Iuan Liu; Chih-Lu Wei; Ting-Kuei Kuan; Shen-Iuan Liu; SHEN-IUAN LIU |
| 臺大學術典藏 |
2018-09-10T15:26:01Z |
A loop gain optimization technique for integer-N TDC-based phase-locked loops
|
Ting-Kuei Kuan;Shen-Iuan Liu; Ting-Kuei Kuan; Shen-Iuan Liu; SHEN-IUAN LIU |
| 臺大學術典藏 |
2018-09-10T15:00:23Z |
An all-digital de-spreading clock generator
|
I-Ting Lee;Shih-Han Ku;Shen-Iuan Liu; I-Ting Lee; Shih-Han Ku; Shen-Iuan Liu; SHEN-IUAN LIU |
| 臺大學術典藏 |
2018-09-10T15:00:23Z |
A 3-25 Gb/s 4-channel receiver with noise-canceling TIA and power scalable LA
|
Yu-Hsun Chien;Kuan-Lin Fu;Shen-Iuan Liu; Yu-Hsun Chien; Kuan-Lin Fu; Shen-Iuan Liu; SHEN-IUAN LIU |
| 臺大學術典藏 |
2018-09-10T15:00:23Z |
Nanopower CMOS relaxation oscillators with sub-100ppm/°C temperature coefficient
|
Yu-Hsuan Chiang;Shen-Iuan Liu; Yu-Hsuan Chiang; Shen-Iuan Liu; SHEN-IUAN LIU |
| 臺大學術典藏 |
2018-09-10T09:50:32Z |
A 300 GHz divide-by-2 ILFD using frequency boosting technique
|
Pin-Hao Feng;Shen-Iuan Liu; Pin-Hao Feng; Shen-Iuan Liu; SHEN-IUAN LIU |
| 臺大學術典藏 |
2018-09-10T09:50:32Z |
A 10-Gb/s adaptive parallel receiver with joint XTC and DFE using power detection
|
Shih-Yuan Kao;Shen-Iuan Liu; Shih-Yuan Kao; Shen-Iuan Liu; SHEN-IUAN LIU |
| 臺大學術典藏 |
2018-09-10T09:50:31Z |
Divide-by-three injection-locked frequency dividers over 200 GHz in 40-nm CMOS
|
Pin-Hao Feng;Shen-Iuan Liu; Pin-Hao Feng; Shen-Iuan Liu; SHEN-IUAN LIU |
| 臺大學術典藏 |
2018-09-10T09:50:31Z |
A 7.5-Gb/s one-tap FFE transmitter with adaptive far-end crosstalk cancellation using duty cycle detection
|
Shih-Yuan Kao;Shen-Iuan Liu; Shih-Yuan Kao; Shen-Iuan Liu; SHEN-IUAN LIU |
| 臺大學術典藏 |
2018-09-10T09:50:31Z |
A 2.4GHz sub-harmonically injection-locked PLL with self-calibrated injection timing
|
SHEN-IUAN LIU; Shen-Iuan Liu; Yi-Chieh Huang; Yi-Chieh Huang;Shen-Iuan Liu |
| 臺大學術典藏 |
2018-09-10T09:50:31Z |
A wide-range PLL using self-healing prescaler/VCO in 65-nm CMOS
|
I-Ting Lee;Yun-Ta Tsai;Shen-Iuan Liu; I-Ting Lee; Yun-Ta Tsai; Shen-Iuan Liu; SHEN-IUAN LIU |
| 臺大學術典藏 |
2018-09-10T09:50:31Z |
4-Gb/s parallel receivers with adaptive far-end crosstalk cancellation
|
Yan-Yu Lin;Shen-Iuan Liu; Yan-Yu Lin; Shen-Iuan Liu; SHEN-IUAN LIU |
| 臺大學術典藏 |
2018-09-10T09:50:31Z |
A 4.8-GHz Dividerless Subharmonically Injection-Locked All-Digital PLL With a FOM of-252.5 dB
|
I-Ting Lee;Kai-Hui Zeng;Shen-Iuan Liu; I-Ting Lee; Kai-Hui Zeng; Shen-Iuan Liu; SHEN-IUAN LIU |
| 臺大學術典藏 |
2018-09-10T09:50:31Z |
4-Gb/s parallel receivers with adaptive FEXT cancellation by pulse-width and amplitude calibrations
|
Yan-Yu Lin;Shen-Iuan Liu; Yan-Yu Lin; Shen-Iuan Liu; SHEN-IUAN LIU |
| 臺大學術典藏 |
2018-09-10T09:50:31Z |
An all-digital spread-spectrum clock generator with self-calibrated bandwidth
|
I-Ting Lee;Shih-Han Ku;Shen-Iuan Liu; I-Ting Lee; Shih-Han Ku; Shen-Iuan Liu; SHEN-IUAN LIU |
| 臺大學術典藏 |
2018-09-10T09:50:31Z |
A current-reused injection-locked frequency multiplication/division circuit in 40-nm CMOS
|
Pin-Hao Feng;Shen-Iuan Liu; Pin-Hao Feng; Shen-Iuan Liu; SHEN-IUAN LIU |
| 臺大學術典藏 |
2018-09-10T09:50:30Z |
A submicrowatt 1.1-MHz CMOS relaxation oscillator with temperature compensation
|
Yu-Hsuan Chiang;Shen-Iuan Liu; Yu-Hsuan Chiang; Shen-Iuan Liu; SHEN-IUAN LIU |
| 臺大學術典藏 |
2018-09-10T09:24:58Z |
A 6.7MHz-to-1.24GHz 0.0318mm 2 fast-locking all-digital DLL in 90nm CMOS
|
Liang-Hsin Chen;Min-Han Hsieh;Shen-Iuan Liu;Charlie Chung-Ping Chen; Liang-Hsin Chen; Min-Han Hsieh; Shen-Iuan Liu; Charlie Chung-Ping Chen; SHEN-IUAN LIU |
| 臺大學術典藏 |
2018-09-10T09:24:58Z |
A 2.4GHz sub-harmonically injection-locked PLL with self-calibrated injection timing
|
SHEN-IUAN LIU; Shen-Iuan Liu; Yi-Chieh Huang; Yi-Chieh Huang;Shen-Iuan Liu |
| 臺大學術典藏 |
2018-09-10T09:24:58Z |
A fast-locking phase-locked loop using CP control and gated VCO
|
I-Ting Lee;Yun-Ta Tsai;Shen-Iuan Liu; I-Ting Lee; Yun-Ta Tsai; Shen-Iuan Liu; SHEN-IUAN LIU |
