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Showing items 51-60 of 264  (27 Page(s) Totally)
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Institution Date Title Author
臺大學術典藏 2020-06-11T06:34:38Z CMOS four-quadrant multiplier using bias offset crosscoupled pairs Liu, S.-I.;Hwang, Y.-S.; Liu, S.-I.; Hwang, Y.-S.; SHEN-IUAN LIU
臺大學術典藏 2020-06-11T06:34:38Z Realisation of R-L and C-D impedances using a current feedback amplifier and its applications Liu, S.-I.;Hwang, Y.-S.; Liu, S.-I.; Hwang, Y.-S.; SHEN-IUAN LIU
臺大學術典藏 2020-06-11T06:34:37Z 258.16-259.95GHz injection-locked frequency divider Lee, I.-T.;Wang, C.-H.;Lin, B.-Y.;Liu, S.-I.; Lee, I.-T.; Wang, C.-H.; Lin, B.-Y.; Liu, S.-I.; SHEN-IUAN LIU
臺大學術典藏 2020-06-11T06:34:37Z Design of a CMOS low-power and low-voltage four-quadrant analog multiplier Liu, W.;Liu, S.-I.; Liu, W.; Liu, S.-I.; SHEN-IUAN LIU
臺大學術典藏 2020-06-11T06:34:36Z 2011 Proceedings of Technical Papers: IEEE Asian Solid-State Circuits Conference 2011, A-SSCC 2011: Foreword Liu, S.-I.; Liu, S.-I.; SHEN-IUAN LIU
臺大學術典藏 2018-09-10T15:26:01Z A subharmonically injection-locked PLL with calibrated injection pulsewidth Chih-Lu Wei;Ting-Kuei Kuan;Shen-Iuan Liu; Chih-Lu Wei; Ting-Kuei Kuan; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏 2018-09-10T15:26:01Z A loop gain optimization technique for integer-N TDC-based phase-locked loops Ting-Kuei Kuan;Shen-Iuan Liu; Ting-Kuei Kuan; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏 2018-09-10T15:00:23Z An all-digital de-spreading clock generator I-Ting Lee;Shih-Han Ku;Shen-Iuan Liu; I-Ting Lee; Shih-Han Ku; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏 2018-09-10T15:00:23Z A 3-25 Gb/s 4-channel receiver with noise-canceling TIA and power scalable LA Yu-Hsun Chien;Kuan-Lin Fu;Shen-Iuan Liu; Yu-Hsun Chien; Kuan-Lin Fu; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏 2018-09-10T15:00:23Z Nanopower CMOS relaxation oscillators with sub-100ppm/°C temperature coefficient Yu-Hsuan Chiang;Shen-Iuan Liu; Yu-Hsuan Chiang; Shen-Iuan Liu; SHEN-IUAN LIU

Showing items 51-60 of 264  (27 Page(s) Totally)
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