| 臺大學術典藏 |
2020-06-11T06:34:38Z |
CMOS four-quadrant multiplier using bias offset crosscoupled pairs
|
Liu, S.-I.;Hwang, Y.-S.; Liu, S.-I.; Hwang, Y.-S.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:38Z |
Realisation of R-L and C-D impedances using a current feedback amplifier and its applications
|
Liu, S.-I.;Hwang, Y.-S.; Liu, S.-I.; Hwang, Y.-S.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:37Z |
258.16-259.95GHz injection-locked frequency divider
|
Lee, I.-T.;Wang, C.-H.;Lin, B.-Y.;Liu, S.-I.; Lee, I.-T.; Wang, C.-H.; Lin, B.-Y.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:37Z |
Design of a CMOS low-power and low-voltage four-quadrant analog multiplier
|
Liu, W.;Liu, S.-I.; Liu, W.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:36Z |
2011 Proceedings of Technical Papers: IEEE Asian Solid-State Circuits Conference 2011, A-SSCC 2011: Foreword
|
Liu, S.-I.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2018-09-10T15:26:01Z |
A subharmonically injection-locked PLL with calibrated injection pulsewidth
|
Chih-Lu Wei;Ting-Kuei Kuan;Shen-Iuan Liu; Chih-Lu Wei; Ting-Kuei Kuan; Shen-Iuan Liu; SHEN-IUAN LIU |
| 臺大學術典藏 |
2018-09-10T15:26:01Z |
A loop gain optimization technique for integer-N TDC-based phase-locked loops
|
Ting-Kuei Kuan;Shen-Iuan Liu; Ting-Kuei Kuan; Shen-Iuan Liu; SHEN-IUAN LIU |
| 臺大學術典藏 |
2018-09-10T15:00:23Z |
An all-digital de-spreading clock generator
|
I-Ting Lee;Shih-Han Ku;Shen-Iuan Liu; I-Ting Lee; Shih-Han Ku; Shen-Iuan Liu; SHEN-IUAN LIU |
| 臺大學術典藏 |
2018-09-10T15:00:23Z |
A 3-25 Gb/s 4-channel receiver with noise-canceling TIA and power scalable LA
|
Yu-Hsun Chien;Kuan-Lin Fu;Shen-Iuan Liu; Yu-Hsun Chien; Kuan-Lin Fu; Shen-Iuan Liu; SHEN-IUAN LIU |
| 臺大學術典藏 |
2018-09-10T15:00:23Z |
Nanopower CMOS relaxation oscillators with sub-100ppm/°C temperature coefficient
|
Yu-Hsuan Chiang;Shen-Iuan Liu; Yu-Hsuan Chiang; Shen-Iuan Liu; SHEN-IUAN LIU |
| 臺大學術典藏 |
2018-09-10T09:50:32Z |
A 300 GHz divide-by-2 ILFD using frequency boosting technique
|
Pin-Hao Feng;Shen-Iuan Liu; Pin-Hao Feng; Shen-Iuan Liu; SHEN-IUAN LIU |
| 臺大學術典藏 |
2018-09-10T09:50:32Z |
A 10-Gb/s adaptive parallel receiver with joint XTC and DFE using power detection
|
Shih-Yuan Kao;Shen-Iuan Liu; Shih-Yuan Kao; Shen-Iuan Liu; SHEN-IUAN LIU |
| 臺大學術典藏 |
2018-09-10T09:50:31Z |
Divide-by-three injection-locked frequency dividers over 200 GHz in 40-nm CMOS
|
Pin-Hao Feng;Shen-Iuan Liu; Pin-Hao Feng; Shen-Iuan Liu; SHEN-IUAN LIU |
| 臺大學術典藏 |
2018-09-10T09:50:31Z |
A 7.5-Gb/s one-tap FFE transmitter with adaptive far-end crosstalk cancellation using duty cycle detection
|
Shih-Yuan Kao;Shen-Iuan Liu; Shih-Yuan Kao; Shen-Iuan Liu; SHEN-IUAN LIU |
| 臺大學術典藏 |
2018-09-10T09:50:31Z |
A 2.4GHz sub-harmonically injection-locked PLL with self-calibrated injection timing
|
SHEN-IUAN LIU; Shen-Iuan Liu; Yi-Chieh Huang; Yi-Chieh Huang;Shen-Iuan Liu |
| 臺大學術典藏 |
2018-09-10T09:50:31Z |
A wide-range PLL using self-healing prescaler/VCO in 65-nm CMOS
|
I-Ting Lee;Yun-Ta Tsai;Shen-Iuan Liu; I-Ting Lee; Yun-Ta Tsai; Shen-Iuan Liu; SHEN-IUAN LIU |
| 臺大學術典藏 |
2018-09-10T09:50:31Z |
4-Gb/s parallel receivers with adaptive far-end crosstalk cancellation
|
Yan-Yu Lin;Shen-Iuan Liu; Yan-Yu Lin; Shen-Iuan Liu; SHEN-IUAN LIU |
| 臺大學術典藏 |
2018-09-10T09:50:31Z |
A 4.8-GHz Dividerless Subharmonically Injection-Locked All-Digital PLL With a FOM of-252.5 dB
|
I-Ting Lee;Kai-Hui Zeng;Shen-Iuan Liu; I-Ting Lee; Kai-Hui Zeng; Shen-Iuan Liu; SHEN-IUAN LIU |
| 臺大學術典藏 |
2018-09-10T09:50:31Z |
4-Gb/s parallel receivers with adaptive FEXT cancellation by pulse-width and amplitude calibrations
|
Yan-Yu Lin;Shen-Iuan Liu; Yan-Yu Lin; Shen-Iuan Liu; SHEN-IUAN LIU |
| 臺大學術典藏 |
2018-09-10T09:50:31Z |
An all-digital spread-spectrum clock generator with self-calibrated bandwidth
|
I-Ting Lee;Shih-Han Ku;Shen-Iuan Liu; I-Ting Lee; Shih-Han Ku; Shen-Iuan Liu; SHEN-IUAN LIU |
| 臺大學術典藏 |
2018-09-10T09:50:31Z |
A current-reused injection-locked frequency multiplication/division circuit in 40-nm CMOS
|
Pin-Hao Feng;Shen-Iuan Liu; Pin-Hao Feng; Shen-Iuan Liu; SHEN-IUAN LIU |
| 臺大學術典藏 |
2018-09-10T09:50:30Z |
A submicrowatt 1.1-MHz CMOS relaxation oscillator with temperature compensation
|
Yu-Hsuan Chiang;Shen-Iuan Liu; Yu-Hsuan Chiang; Shen-Iuan Liu; SHEN-IUAN LIU |
| 臺大學術典藏 |
2018-09-10T09:24:58Z |
A 6.7MHz-to-1.24GHz 0.0318mm 2 fast-locking all-digital DLL in 90nm CMOS
|
Liang-Hsin Chen;Min-Han Hsieh;Shen-Iuan Liu;Charlie Chung-Ping Chen; Liang-Hsin Chen; Min-Han Hsieh; Shen-Iuan Liu; Charlie Chung-Ping Chen; SHEN-IUAN LIU |
| 臺大學術典藏 |
2018-09-10T09:24:58Z |
A 2.4GHz sub-harmonically injection-locked PLL with self-calibrated injection timing
|
SHEN-IUAN LIU; Shen-Iuan Liu; Yi-Chieh Huang; Yi-Chieh Huang;Shen-Iuan Liu |
| 臺大學術典藏 |
2018-09-10T09:24:58Z |
A fast-locking phase-locked loop using CP control and gated VCO
|
I-Ting Lee;Yun-Ta Tsai;Shen-Iuan Liu; I-Ting Lee; Yun-Ta Tsai; Shen-Iuan Liu; SHEN-IUAN LIU |
