臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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	2019臺灣學術機構典藏研討會
	機構典藏系統RC7版本已發佈

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Showing items 76-100 of 264 (11 Page(s) Totally)
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Institution	Date	Title	Author
臺大學術典藏	2018-09-10T09:24:58Z	A 20Gb/s adaptive duobinary transceiver	Yu-Ming Ying;I-Ting Lee;Shen-Iuan Liu; Yu-Ming Ying; I-Ting Lee; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T09:24:57Z	A 104GHz phase-locked loop using a VCO at second pole frequency	Kun-Hung Tsai;Shen-Iuan Liu; Kun-Hung Tsai; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T09:24:57Z	Inductorless wideband CMOS low-noise amplifiers using noise-canceling technique	Ke-Hou Chen;Shen-Iuan Liu; Ke-Hou Chen; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T09:24:57Z	G-Band injection-locked frequency dividers using π-type LC Network	I-Ting Lee;Shen-Iuan Liu; I-Ting Lee; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T09:24:57Z	A 3.6mW 125.7~131.86GHz divide-by-4 injection-locked frequency divider in 90nm CMOS	I-Ting Lee;Chiao-Hsing Wang;Chun-Lin Ko;Ying-Zong Juang;Shen-Iuan Liu; I-Ting Lee; Chiao-Hsing Wang; Chun-Lin Ko; Ying-Zong Juang; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T09:24:57Z	An all-digital jitter-tolerance measurement technique for CDR circuits	Yi-Chieh Huang;Ping-Ying Wang;Shen-Iuan Liu; Yi-Chieh Huang; Ping-Ying Wang; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T09:24:57Z	A 6GHz all-digital fractional-N frequency synthesizer using FIR-embedded noise filtering technique	I-Ting Lee;Hung-Yu Lu;Shen-Iuan Liu; I-Ting Lee; Hung-Yu Lu; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T09:24:57Z	A D-band divide-by-3 injection-locked frequency divider in 65nm CMOS	I-Ting Lee;Chiao-Hsing Wang;Ju-Rong Sha;Ying-Zong Juang;Shen-Iuan Liu; I-Ting Lee; Chiao-Hsing Wang; Ju-Rong Sha; Ying-Zong Juang; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T09:24:57Z	A leakage-current-recycling phase-locked loop in 65nm CMOS technology	I-Ting Lee;Yun-Ta Tsai;Shen-Iuan Liu; I-Ting Lee; Yun-Ta Tsai; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T08:46:29Z	A leakage-current-recycling phase-locked loop in 65nm CMOS technology	I-Ting Lee; Yun-Ta Tsai; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T08:46:29Z	Low voltage Pipelined Analog-to-Digital Converter	?B?`?W; ¼B²`²W; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T08:46:28Z	A rail-to-rail class-B buffer with DC level-shifting current mirror and distributed Miller compensation for LCD column drivers	Wei-Jen Huang; Shigeisa Nagayasu; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T08:46:28Z	A current-reused divide-by-3 injection-locked frequency divider in 65nm CMOS	I-Ting Lee; Chiao-Hsing Wang; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T08:46:28Z	Decision feedback equalizers using back-gate feedback technique	Chang-Lin Hsieh; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T08:46:27Z	A PSRR-enhanced low-dropout regulator	Wei-Jen Huang; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T08:46:27Z	A noise-filtering technique for fractional-N frequency synthesizers	Chao-Ching Hung; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T08:46:27Z	A digitally-calibrated phase-locked loop with supply sensitivity suppression	Shih-Yuan Kao; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T08:46:27Z	Analysis and design of D-band injection-locked frequency dividers	Bo-Yu Lin; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T08:46:27Z	A 40-GHz fast-locked all-digital phase-locked loop using a modified bang-bang algorithm	Chao-Ching Hung; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T08:18:17Z	A 35.56GHz all-digital phase-locked loop with high resolution varactors	Chao-Ching Hung;Shen-Iuan Liu; Chao-Ching Hung; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T08:18:17Z	A 198.9GHz ~201.0GHz injection-locked frequency divider in 65nm CMOS	Bo-Yu Lin;I-Ting Lee;Chiao-Hsing Wang;Shen-Iuan Liu; Bo-Yu Lin; I-Ting Lee; Chiao-Hsing Wang; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T08:18:16Z	A 1.62/2.7-Gb/s adaptive transmitter with two-tap preemphasis using a propagation-time detector	Shih-Yuan Kao;Shen-Iuan Liu; Shih-Yuan Kao; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T08:18:16Z	A 20Gbps transmitter with adaptive pre-emphasis in 65nm CMOS technology	Shih-Yuan Kao;Shen-Iuan Liu; Shih-Yuan Kao; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T08:18:16Z	A phase-locked loop with background leakage current compensation	Jung-Yu Chang;Shen-Iuan Liu; Jung-Yu Chang; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T08:18:16Z	A 258.16~259.95 GHz injection-locked frequency divider	I-Ting Lee;Chiao-Hsing Wang;Bo-Yu Lin,;Shen-Iuan Liu; I-Ting Lee; Chiao-Hsing Wang; Bo-Yu Lin,; Shen-Iuan Liu; SHEN-IUAN LIU

Showing items 76-100 of 264 (11 Page(s) Totally)
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