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Institution	Date	Title	Author
元智大學	2017-11-12	Overview of the 2017 CAD Contest at ICCAD	Myung-Chul Kim; Shih-Hsu Huang; Lin R.-B.; Shigetoshi Nakatake
元智大學	2016-11-07	Overview of the 2016 CAD Contest at ICCAD	Shih-Hsu Huang; Lin R.-B.; Myung-Chul Kim; Shigetoshi Nakatake
中原大學	2010-05	Minimum buffer insertions for clock period minimization	Shih-Hsu Huang;Guan-Yu Jhuo;Wei-Lun Huang
中原大學	2010-05	A Design Partitioning Algorithm for Three Dimensional Integrated Circuits	Hua-Sin Ye;Mely Chen Chi;Shih-Hsu Huang
中原大學	2010-05	A Post-Processing Approach to Minimize TSV Number for High-Level Synthesis of 3D ICs	Chih-Hung Lee;Tsorng-Yu Huang;Chun-Hua Cheng;Shih-Hsu Huang
中原大學	2009-11	Synthesis of Anti-Aging Gated Clock Designs	Shih-Hsu Huang; Chun-Hua Cheng; Song-Bin Pan
中原大學	2009-11	Simultaneous Clock Skew Scheduling and Power-Gated Module Selection for Standby Leakage Minimization	Shih-Hsu Huang; Chun-Hua Cheng; Da-Chen Tzeng
中原大學	2009-08	Minimum-Period Register Binding	Shih-Hsu Huang; Chun-Hua Cheng
中原大學	2009-07-25	An ILP Approach to Surge Current Minimization in High-Level Synthesis	Shih-Hsu Huang; Jheng-Fu Yeh; Chun-Hua Cheng
中原大學	2009-06	Post-Floorplan Power Distribution Network Design for 3D ICs	Yalamandala Raghu;Chun-Hua Cheng;Shih-Hsu Huang
中原大學	2009-05	MINIMUM-POWER CLOCK GATING	Jia-Hong Jian; Chun-Hua Cheng; Chia-Ming Chang; Shih-Hsu Huang
中原大學	2009-01	Opposite-Phase Register Switching for Peak Current Minimization	Shih-Hsu Huang; Chia-Ming Chang; Yow-Tyng Nieh
中原大學	2008-04-01	Opposite-phase scheme for peak current reduction	Yow-Tyng Nieh;Sheng-Yu Hsu;Shih-Hsu Huang;Yeong-Jar Chang
中原大學	2007	Opposite-Phase Clock Tree for Peak Current Reduction	Yow-Tyng Nieh;Shih-Hsu Huang;Sheng-Yu Hsu
中原大學	2004-11	An Effective Approach to Designing a Power Distribution Network at the Post-Floorplan Stage	Shih-Hsu Huang;Yow-Tyng Nieh;Chu-Liao Wang
中原大學	2004-09	Design Automation of Fuzzy Rules Based on Trapezoid-Shaped Membership Functions	Shih-Hsu Huang;Wen-Hon Peng;Shi-Zhi Liu;Jian-Yuan Lai
中原大學	2004-09	Performance and Power Driven Non-Zero Skew Clock Tree Design Methodology	Shih-Hsu Huang;Yow-Tyng Nieh;Yu-Hui Lin
中原大學	2004-06	A Timing Driven Crosstalk Optimizer for Gridded Channel Routing	Shih-Hsu Huang;Yi-Siang Hsu;Chiu-Cheng Lin
中原大學	2001-03	A Practical Interconnect-Driven Design Methodology for Low Power ASIC Designs	Shih-Hsu Huang;Mely Chen Chi;Hsu-Ming Hsiao
中原大學	2001	A Practical Interconnect-Driven Design Methodology For Low Power ASIC Designs	Shih-Hsu Huang;Mely Chen Chi;Hsu-Ming Hsiao
中原大學	2001	An Efficient Membership Function Representation For High-Resolution Fuzzy Systems	Shih-Hsu Huang;Jian-Yuan Lai
中原大學	2000-09	A Reliable Clock Tree Design Methodology for ASIC Designs	Mely Chen Chi;Shih-Hsu Huang
中原大學	2000	A Reliable Clock Tree Design Methodology for ASIC Designs	Mely Chen Chi;Shih-Hsu Huang
中原大學	1995	A New Approach to Schedule Operations across Nested-ifs and Nested-loops	Shih-Hsu Huang;Cheng-Tsung Hwang;Yu-Chin Hsu;Yen-Jen Oyang
中原大學	1995	A New Scheduling Algorithm for Synthesizing the Control Blocks of Control-Dominated Circuits	Shih-Hsu Huang;Yu-Chin Hsu;Yen-Jen Oyang

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