臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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Institution	Date	Title	Author
元智大學	2017-11-12	Overview of the 2017 CAD Contest at ICCAD	Myung-Chul Kim; Shih-Hsu Huang; Lin R.-B.; Shigetoshi Nakatake
元智大學	2016-11-07	Overview of the 2016 CAD Contest at ICCAD	Shih-Hsu Huang; Lin R.-B.; Myung-Chul Kim; Shigetoshi Nakatake
中原大學	2010-05	Minimum buffer insertions for clock period minimization	Shih-Hsu Huang;Guan-Yu Jhuo;Wei-Lun Huang
中原大學	2010-05	A Design Partitioning Algorithm for Three Dimensional Integrated Circuits	Hua-Sin Ye;Mely Chen Chi;Shih-Hsu Huang
中原大學	2010-05	A Post-Processing Approach to Minimize TSV Number for High-Level Synthesis of 3D ICs	Chih-Hung Lee;Tsorng-Yu Huang;Chun-Hua Cheng;Shih-Hsu Huang
中原大學	2009-11	Synthesis of Anti-Aging Gated Clock Designs	Shih-Hsu Huang; Chun-Hua Cheng; Song-Bin Pan
中原大學	2009-11	Simultaneous Clock Skew Scheduling and Power-Gated Module Selection for Standby Leakage Minimization	Shih-Hsu Huang; Chun-Hua Cheng; Da-Chen Tzeng
中原大學	2009-08	Minimum-Period Register Binding	Shih-Hsu Huang; Chun-Hua Cheng
中原大學	2009-07-25	An ILP Approach to Surge Current Minimization in High-Level Synthesis	Shih-Hsu Huang; Jheng-Fu Yeh; Chun-Hua Cheng
中原大學	2009-06	Post-Floorplan Power Distribution Network Design for 3D ICs	Yalamandala Raghu;Chun-Hua Cheng;Shih-Hsu Huang

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