|
English
|
正體中文
|
简体中文
|
總筆數 :0
|
|
造訪人次 :
52691555
線上人數 :
1090
教育部委託研究計畫 計畫執行:國立臺灣大學圖書館
|
|
|
"shih timothy k"的相關文件
顯示項目 466-475 / 479 (共48頁)
<< < 39 40 41 42 43 44 45 46 47 48 > >>
每頁顯示[10|25|50]項目
| 淡江大學 |
1994-12 |
Spec: A Specification Processing Environment with Controls
|
施國琛; Shih, Timothy K.; Davis, Ruth E. |
| 淡江大學 |
1994-09 |
A Temporal Arithmetic Based Reasoning System for Systolic Array Designs
|
施國琛; Shih, Timothy K.; Ling, Nam |
| 淡江大學 |
1994 |
Formalizing the design of systolic array designs
|
施國琛; Shih, Timothy K. |
| 淡江大學 |
1993-08 |
VSTA : a prolog-based formal verifier for systolic array designs
|
Ling, Nam; 施國琛; Shih, Timothy K. |
| 淡江大學 |
1993-08 |
The use of fixed point induction in verifying systolic array designs : An applicative approach
|
施國琛; Shih, Timothy K. |
| 淡江大學 |
1993-01 |
Verification of systolic architecture designs
|
施國琛 ; Shih, Timothy K. |
| 淡江大學 |
1992-10 |
The specification and verification of synchronous concurrent computation
|
Lin, F.; 施國琛; Shih, Timothy K.; Lin, H. ; Wang, H. |
| 淡江大學 |
1992-01 |
Coping with failure : disciplined exception handling in logic programming
|
施國琛; Shih, Timothy K. |
| 淡江大學 |
1992-01 |
Inductive techniques for formal verification of systolic array designs in DSP applications approach
|
施國琛; Shih, Timothy K. |
| 淡江大學 |
1992-01 |
Intelligence backstracking and controls based on a deduction status representation in logic programming
|
施國琛; Shih, Timothy K. |
顯示項目 466-475 / 479 (共48頁)
<< < 39 40 41 42 43 44 45 46 47 48 > >>
每頁顯示[10|25|50]項目
|
