臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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Institution	Date	Title	Author
臺大學術典藏	2018-09-10T15:23:15Z	Buffered clock tree synthesis considering self-heating effects	Lin, C.-W.;Hsu, T.-H.;Shih, X.-W.;Chang, Y.-W.; Lin, C.-W.; Hsu, T.-H.; Shih, X.-W.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T15:23:15Z	Buffered clock tree synthesis considering self-heating effects	Lin, C.-W.;Hsu, T.-H.;Shih, X.-W.;Chang, Y.-W.; Lin, C.-W.; Hsu, T.-H.; Shih, X.-W.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T14:57:59Z	Buffered clock tree synthesis considering self-heating effects	Lin, C.-W.;Hsu, T.-H.;Shih, X.-W.;Chang, Y.-W.; Lin, C.-W.; Hsu, T.-H.; Shih, X.-W.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T14:57:59Z	Buffered clock tree synthesis considering self-heating effects	Lin, C.-W.;Hsu, T.-H.;Shih, X.-W.;Chang, Y.-W.; Lin, C.-W.; Hsu, T.-H.; Shih, X.-W.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T09:48:07Z	Layer minimization in escape routing for staggered-pin-array PCBs	Ho, Y.-K.;Shih, X.-W.;Chang, Y.-W.;Cheng, C.-K.; Ho, Y.-K.; Shih, X.-W.; Chang, Y.-W.; Cheng, C.-K.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T09:48:07Z	Layer minimization in escape routing for staggered-pin-array PCBs	Ho, Y.-K.;Shih, X.-W.;Chang, Y.-W.;Cheng, C.-K.; Ho, Y.-K.; Shih, X.-W.; Chang, Y.-W.; Cheng, C.-K.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T09:48:07Z	Symmetrical buffered clock-tree synthesis with supply-voltage alignment	Shih, X.-W.;Hsu, T.-H.;Lee, H.-C.;Chang, Y.-W.;Chao, K.-Y.; Shih, X.-W.; Hsu, T.-H.; Lee, H.-C.; Chang, Y.-W.; Chao, K.-Y.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T09:48:07Z	Symmetrical buffered clock-tree synthesis with supply-voltage alignment	Shih, X.-W.;Hsu, T.-H.;Lee, H.-C.;Chang, Y.-W.;Chao, K.-Y.; Shih, X.-W.; Hsu, T.-H.; Lee, H.-C.; Chang, Y.-W.; Chao, K.-Y.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T09:22:26Z	Fast timing-model independent buffered clock-tree synthesis	Shih, X.-W.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T08:14:58Z	Blockage-avoiding buffered clock-tree synthesis for clock latency-range and skew minimization	Shih, X.-W.; Cheng, C.-C.; Ho, Y.-K.; Chang, Y.-W.; Shih, X.-W.; Cheng, C.-C.; Ho, Y.-K.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T08:14:58Z	Blockage-avoiding buffered clock-tree synthesis for clock latency-range and skew minimization	Shih, X.-W.; Cheng, C.-C.; Ho, Y.-K.; Chang, Y.-W.; Shih, X.-W.; Cheng, C.-C.; Ho, Y.-K.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T08:14:57Z	Fast timing-model independent buffered clock-tree synthesis	Shih, X.-W.; Chang, Y.-W.; Shih, X.-W.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T08:14:57Z	Fast timing-model independent buffered clock-tree synthesis	Shih, X.-W.; Chang, Y.-W.; Shih, X.-W.; Chang, Y.-W.; YAO-WEN CHANG

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