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Showing items 11-13 of 13 (2 Page(s) Totally)
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| 臺大學術典藏 |
2018-09-10T08:14:58Z |
Blockage-avoiding buffered clock-tree synthesis for clock latency-range and skew minimization
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Shih, X.-W.; Cheng, C.-C.; Ho, Y.-K.; Chang, Y.-W.; Shih, X.-W.; Cheng, C.-C.; Ho, Y.-K.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T08:14:57Z |
Fast timing-model independent buffered clock-tree synthesis
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Shih, X.-W.; Chang, Y.-W.; Shih, X.-W.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T08:14:57Z |
Fast timing-model independent buffered clock-tree synthesis
|
Shih, X.-W.; Chang, Y.-W.; Shih, X.-W.; Chang, Y.-W.; YAO-WEN CHANG |
Showing items 11-13 of 13 (2 Page(s) Totally)
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