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Taiwan Academic Institutional Repository >
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"su k w"
Showing items 121-130 of 130 (6 Page(s) Totally)
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| 國立臺灣大學 |
1995-09 |
A high-speed 1.5 V clocked BiCMOS latch for BiCMOS dynamic pipelined digital logic VLSI systems
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Kuo, J.B.; Lou, J.H.; Su, K.W. |
| 臺大學術典藏 |
1995-09 |
A high-speed 1.5 V clocked BiCMOS latch for BiCMOS dynamic pipelined digital logic VLSI systems
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Kuo, J.B.; Lou, J.H.; Su, K.W.; Kuo, J.B.; Lou, J.H.; Su, K.W.; KuoJB |
| 國立臺灣大學 |
1994-12 |
A 1.5 V 10 MHz BiCMOS quasi-digital vector modulator for wireless communication IC
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Su, K.W.; Chen, Y.G.; Lai, C.S.; Kuo, J.B.; Wu, J.S.; Tso, H.W. |
| 國立臺灣大學 |
1994-06 |
A BiCMOS dynamic multiplier using Wallace tree reduction architecture and 1.5 V full-swing BiCMOS dynamic logic circuit
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Kuo, J.B.; Su, K.W.; Lou, J.H. |
| 臺大學術典藏 |
1994-06 |
A BiCMOS dynamic multiplier using Wallace tree reduction architecture and 1.5 V full-swing BiCMOS dynamic logic circuit
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Kuo, J.B.; Su, K.W.; Lou, J.H.; Kuo, J.B.; Su, K.W.; Lou, J.H.; KuoJB |
| 國立臺灣大學 |
1994-05 |
Device-level analysis of a BiPMOS pull-down device structure for low-voltage dynamic BiCMOS VLSI
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Kuo, J.B.; Su, K.W.; Lou, J.H.; Ma, Y.; Chen, S.S.; Chiang, C.S. |
| 臺大學術典藏 |
1994-05 |
Device-level analysis of a BiPMOS pull-down device structure for low-voltage dynamic BiCMOS VLSI
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Kuo, J.B.; Su, K.W.; Lou, J.H.; Ma, Y.; Chen, S.S.; Chiang, C.S.; Kuo, J.B.; Su, K.W.; Lou, J.H.; Ma, Y.; Chen, S.S.; Chiang, C.S.; KuoJB |
| 國立臺灣大學 |
1993-11 |
1.5V BiCMOS dynamic multiplier using Wallace tree reduction architecture
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Kuo, J.B.; Su, K.W.; Lou, J.H. |
| 臺大學術典藏 |
1993-11 |
1.5V BiCMOS dynamic multiplier using Wallace tree reduction architecture
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KuoJB; Su, K.W.; Lou, J.H.; Kuo, J.B.; Kuo, J.B.; Su, K.W.; Lou, J.H. |
| 國立臺灣大學 |
1993-03 |
BiCMOS dynamic minimum circuit using a parallel comparison algorithm for fuzzy controllers
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Chen, S.S.; Chiang, C.S.; Su, K.W.; Kuo, J.B. |
Showing items 121-130 of 130 (6 Page(s) Totally)
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