| 國立成功大學 |
2022-11-22 |
Developing a shortened version of the dementia knowledge assessment scale (DKAS-TC) with a sample in Taiwan: an item response theory approach
|
Hung;Su-Pin;Liao;Yi-Han;Eccleston;Claire;Ku;Elizabeth, Li-Jung |
| 國立成功大學 |
2022-10 |
Forced-Choice Ranking Models for Raters' Ranking Data
|
Hung;Su-Pin;Huang;Hung-Yu |
| 國立成功大學 |
2020-10-31 |
Development and validation of the prenatal activity restriction stress questionnaire: a Rasch rating scale analysis
|
Hung;Hsiao-Ying;Hung;Su-Pin;Chang;Ying-Ju |
| 國立交通大學 |
2020-10-05T02:01:30Z |
A Comprehensive Kinetical Modeling of Polymorphic Phase Distribution of Ferroelectric-Dielectrics and Interfacial Energy Effects on Negative Capacitance FETs
|
Kao, Y-C; Modolo, N.; Su, C-J; Wu, T. L.; Kao, K-H; Wu, P-J; Hsaio, S-W; Useinov, A.; Su, Pin; Wu, W. F.; Huang, G-W; Shieh, J-M; Yeh, W-K; Wang, Y-H; Fang, C-L; Tang, Y-T |
| 國立交通大學 |
2020-10-05T02:01:28Z |
Electrostatic Integrity in Negative-Capacitance FETs - A Subthreshold Modeling Approach
|
Su, Pin; You, Wei-Xiang |
| 國立交通大學 |
2020-03-02T03:23:33Z |
Investigation of Inversion Charge Characteristics and Inversion Charge Loss for InGaAs Negative-Capacitance Double-Gate FinFETs Considering Quantum Capacitance
|
Huang, Shih-En; Lin, Shih-Han; Su, Pin |
| 國立交通大學 |
2020-03-01 |
Variability Analysis for Ferroelectric FET Nonvolatile Memories Considering Random Ferroelectric-Dielectric Phase Distribution
|
Liu, You-Sheng; Su, Pin |
| 國立交通大學 |
2020-02-02T23:55:33Z |
Evaluation of 2D Negative-Capacitance FETs for Low-Voltage SRAM Applications
|
Tseng, Kuei-Yang; You, Wei-Xiang; Su, Pin |
| 國立交通大學 |
2020-02-02T23:55:33Z |
Impact of Multi-Domain Interaction on ON-State Characteristics of MFIS-Type 2D Negative-Capacitance FETs
|
Lu, Po-Sheng; Lin, Chia-Chen; Su, Pin |
| 國立交通大學 |
2020-02-02T23:55:33Z |
Device Structural Effects, SPICE Modeling and Circuit Evaluation for Negative-Capacitance FETs
|
Su, Pin; You, Wei-Xiang |
| 國立交通大學 |
2020-01-02T00:03:29Z |
Investigation of Ferroelectric Granularity for Double-Gate Negative-Capacitance FETs Considering Position and Number Fluctuations
|
Fan, Che-Lun; Tseng, Kuei-Yang; Liu, You-Sheng; Su, Pin |
| 國立交通大學 |
2020-01-01 |
A New 8T Hybrid Nonvolatile SRAM With Ferroelectric FET
|
Hu, Chenming; Su, Pin; You, Wei-Xiang |
| 國立交通大學 |
2019-12-13T01:12:54Z |
Benchmarking of Monolayer and Bilayer Two-Dimensional Transition Metal Dichalcogenide (TMD) Based Logic Circuits and 6T SRAM Cells
|
Yu, Chang-Hung; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2019-10-05T00:08:43Z |
Depolarization Field in Ferroelectric Nonvolatile Memory Considering Minor Loop Operation
|
You, Wei-Xiang; Su, Pin |
| 國立交通大學 |
2019-08-02T02:18:32Z |
Investigation of Fin-Width Sensitivity of Threshold Voltage for InGaAs and Si Negative-Capacitance FinFETs Considering Quantum-Confinement Effect
|
Huang, Shih-En; Yu, Chien-Lin; Su, Pin |
| 國立交通大學 |
2019-05-02T00:26:47Z |
Evaluation of NC-FinFET Based Subsystem-Level Logic Circuits Using SPICE Simulation
|
You, Wei-Xiang; Su, Pin; Hu, Chenming |
| 國立交通大學 |
2019-05-02T00:26:47Z |
Investigation of Short-Channel Effects in 2D Negative-Capacitance Field-Effect Transistors
|
You, Wei-Xiang; Tsai, Chih-Peng; Su, Pin |
| 國立交通大學 |
2019-05-02T00:26:47Z |
Device Structural Effects on Negative-Capacitance FETs
|
Su, Pin; You, Wei-Xiang |
| 國立交通大學 |
2019-05-02T00:25:52Z |
Evaluation of NC-FinFET Based Subsystem-Level Logic Circuits
|
You, Wei-Xiang; Su, Pin; Hu, Chenming |
| 國立交通大學 |
2019-04-03T06:44:23Z |
New Findings on the Drain-Induced Barrier Lowering Characteristics for Tri-Gate Germanium-on-Insulator p-MOSFETs
|
Wu, Shu-Hua; Yu, Chang-Hung; Su, Pin |
| 國立交通大學 |
2019-04-03T06:42:08Z |
Evaluation of Monolithic 3-D Logic Circuits and 6T SRAMs With InGaAs-n/Ge-p Ultra-Thin-Body MOSFETs
|
Yu, Kuan-Chin; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2019-04-03T06:35:52Z |
Theoretical Investigation of DIBL Characteristics for Scaled Tri-Gate InGaAs-OI n-MOSFETs Including Sensitivity to Process Variations
|
Wu, Shu-Hua; Yu, Chien-Lin; Yu, Chang-Hung; Su, Pin |
| 國立交通大學 |
2019-04-02T06:04:45Z |
Exploration and Evaluation of Low-Dropout Linear Voltage Regulator with FinFET, TFET and Hybrid TFET-FinFET Implementations.
|
Chang, Chia-Ning; Chen, Yin-Nien; Huang, Po-Tsang; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2019-04-02T06:04:21Z |
A New and Simple DC Method for Thermal-Resistance Extraction of Scaled FinFET Devices
|
Huang, Wei-Cheng; Su, Pin |
| 國立交通大學 |
2019-04-02T06:04:21Z |
Interface Discrete Trap Induced Variability for Negative Capacitance FinFETs
|
Lee, Ho-Pei; Tseng, Kuei-Yang; Su, Pin |
