| 國立成功大學 |
2022-11-22 |
Developing a shortened version of the dementia knowledge assessment scale (DKAS-TC) with a sample in Taiwan: an item response theory approach
|
Hung;Su-Pin;Liao;Yi-Han;Eccleston;Claire;Ku;Elizabeth, Li-Jung |
| 國立成功大學 |
2022-10 |
Forced-Choice Ranking Models for Raters' Ranking Data
|
Hung;Su-Pin;Huang;Hung-Yu |
| 國立成功大學 |
2020-10-31 |
Development and validation of the prenatal activity restriction stress questionnaire: a Rasch rating scale analysis
|
Hung;Hsiao-Ying;Hung;Su-Pin;Chang;Ying-Ju |
| 國立交通大學 |
2020-10-05T02:01:30Z |
A Comprehensive Kinetical Modeling of Polymorphic Phase Distribution of Ferroelectric-Dielectrics and Interfacial Energy Effects on Negative Capacitance FETs
|
Kao, Y-C; Modolo, N.; Su, C-J; Wu, T. L.; Kao, K-H; Wu, P-J; Hsaio, S-W; Useinov, A.; Su, Pin; Wu, W. F.; Huang, G-W; Shieh, J-M; Yeh, W-K; Wang, Y-H; Fang, C-L; Tang, Y-T |
| 國立交通大學 |
2020-10-05T02:01:28Z |
Electrostatic Integrity in Negative-Capacitance FETs - A Subthreshold Modeling Approach
|
Su, Pin; You, Wei-Xiang |
| 國立交通大學 |
2020-03-02T03:23:33Z |
Investigation of Inversion Charge Characteristics and Inversion Charge Loss for InGaAs Negative-Capacitance Double-Gate FinFETs Considering Quantum Capacitance
|
Huang, Shih-En; Lin, Shih-Han; Su, Pin |
| 國立交通大學 |
2020-03-01 |
Variability Analysis for Ferroelectric FET Nonvolatile Memories Considering Random Ferroelectric-Dielectric Phase Distribution
|
Liu, You-Sheng; Su, Pin |
| 國立交通大學 |
2020-02-02T23:55:33Z |
Evaluation of 2D Negative-Capacitance FETs for Low-Voltage SRAM Applications
|
Tseng, Kuei-Yang; You, Wei-Xiang; Su, Pin |
| 國立交通大學 |
2020-02-02T23:55:33Z |
Impact of Multi-Domain Interaction on ON-State Characteristics of MFIS-Type 2D Negative-Capacitance FETs
|
Lu, Po-Sheng; Lin, Chia-Chen; Su, Pin |
| 國立交通大學 |
2020-02-02T23:55:33Z |
Device Structural Effects, SPICE Modeling and Circuit Evaluation for Negative-Capacitance FETs
|
Su, Pin; You, Wei-Xiang |
| 國立交通大學 |
2020-01-02T00:03:29Z |
Investigation of Ferroelectric Granularity for Double-Gate Negative-Capacitance FETs Considering Position and Number Fluctuations
|
Fan, Che-Lun; Tseng, Kuei-Yang; Liu, You-Sheng; Su, Pin |
| 國立交通大學 |
2020-01-01 |
A New 8T Hybrid Nonvolatile SRAM With Ferroelectric FET
|
Hu, Chenming; Su, Pin; You, Wei-Xiang |
| 國立交通大學 |
2019-12-13T01:12:54Z |
Benchmarking of Monolayer and Bilayer Two-Dimensional Transition Metal Dichalcogenide (TMD) Based Logic Circuits and 6T SRAM Cells
|
Yu, Chang-Hung; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2019-10-05T00:08:43Z |
Depolarization Field in Ferroelectric Nonvolatile Memory Considering Minor Loop Operation
|
You, Wei-Xiang; Su, Pin |
| 國立交通大學 |
2019-08-02T02:18:32Z |
Investigation of Fin-Width Sensitivity of Threshold Voltage for InGaAs and Si Negative-Capacitance FinFETs Considering Quantum-Confinement Effect
|
Huang, Shih-En; Yu, Chien-Lin; Su, Pin |
| 國立交通大學 |
2019-05-02T00:26:47Z |
Evaluation of NC-FinFET Based Subsystem-Level Logic Circuits Using SPICE Simulation
|
You, Wei-Xiang; Su, Pin; Hu, Chenming |
| 國立交通大學 |
2019-05-02T00:26:47Z |
Investigation of Short-Channel Effects in 2D Negative-Capacitance Field-Effect Transistors
|
You, Wei-Xiang; Tsai, Chih-Peng; Su, Pin |
| 國立交通大學 |
2019-05-02T00:26:47Z |
Device Structural Effects on Negative-Capacitance FETs
|
Su, Pin; You, Wei-Xiang |
| 國立交通大學 |
2019-05-02T00:25:52Z |
Evaluation of NC-FinFET Based Subsystem-Level Logic Circuits
|
You, Wei-Xiang; Su, Pin; Hu, Chenming |
| 國立交通大學 |
2019-04-03T06:44:23Z |
New Findings on the Drain-Induced Barrier Lowering Characteristics for Tri-Gate Germanium-on-Insulator p-MOSFETs
|
Wu, Shu-Hua; Yu, Chang-Hung; Su, Pin |
| 國立交通大學 |
2019-04-03T06:42:08Z |
Evaluation of Monolithic 3-D Logic Circuits and 6T SRAMs With InGaAs-n/Ge-p Ultra-Thin-Body MOSFETs
|
Yu, Kuan-Chin; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2019-04-03T06:35:52Z |
Theoretical Investigation of DIBL Characteristics for Scaled Tri-Gate InGaAs-OI n-MOSFETs Including Sensitivity to Process Variations
|
Wu, Shu-Hua; Yu, Chien-Lin; Yu, Chang-Hung; Su, Pin |
| 國立交通大學 |
2019-04-02T06:04:45Z |
Exploration and Evaluation of Low-Dropout Linear Voltage Regulator with FinFET, TFET and Hybrid TFET-FinFET Implementations.
|
Chang, Chia-Ning; Chen, Yin-Nien; Huang, Po-Tsang; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2019-04-02T06:04:21Z |
A New and Simple DC Method for Thermal-Resistance Extraction of Scaled FinFET Devices
|
Huang, Wei-Cheng; Su, Pin |
| 國立交通大學 |
2019-04-02T06:04:21Z |
Interface Discrete Trap Induced Variability for Negative Capacitance FinFETs
|
Lee, Ho-Pei; Tseng, Kuei-Yang; Su, Pin |
| 國立交通大學 |
2019-04-02T06:00:45Z |
Intrinsic Difference Between 2-D Negative-Capacitance FETs With Semiconductor-on-Insulator and Double-Gate Structures
|
You, Wei-Xiang; Su, Pin |
| 國立交通大學 |
2019-04-02T05:59:08Z |
Analysis of Ultra-Thin-Body SOI Subthreshold SRAM Considering Line-Edge Roughness, Work Function Variation, and Temperature Sensitivity
|
Hu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2019-04-02T05:58:35Z |
Experimental Analysis of Quasi-Ballistic Transport in Advanced Si nFinFETs Using New Extraction Method
|
Lin, Ming-Huei; Su, Pin; Chen, Hou-Yu; Lu, Jen-Hsiang; Chang, Vincent S.; Yang, Shyh-Horng |
| 國立交通大學 |
2019-04-02T05:58:12Z |
Analysis of Single-Trap-Induced Random Telegraph Noise on FinFET Devices, 6T SRAM Cell, and Logic Circuits
|
Fan, Ming-Long; Hu, Vita Pi-Ho; Chen, Yin-Nien; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2019-04-02T05:58:09Z |
Variability Analysis of Sense Amplifier for FinFET Subthreshold SRAM Applications
|
Fan, Ming-Long; Hu, Vita Pi-Ho; Chen, Yin-Nien; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2018-08-21T05:56:55Z |
Ultra-Low Voltage Mixed TFET-MOSFET 8T SRAM Cell
|
Chen, Yin-Nien; Fan, Ming-Long; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2018-08-21T05:56:52Z |
Impacts of Work Function Variation and Line Edge Roughness on Hybrid TFET-MOSFET Monolithic 3D SRAMs
|
Wang, Jian-Hao; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2018-08-21T05:56:52Z |
Evaluation of Analog Performance of Monolayer and Bilayer Two-Dimensional Transition Metal Dichalcogenide (TMD) MOSFETs
|
Lee, Hung-Yi; Yu, Chang-Hung; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2018-08-21T05:56:52Z |
Performance Evaluation of Pass-Transistor-Based Circuits using Monolayer and Bilayer 2-D Transition Metal Dichalcogenide (TMD) MOSFETs for 5.9nm Node
|
Yu, Chang-Hung; Zheng, Jun-Teng; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2018-08-21T05:56:52Z |
Investigation and Comparison of Design Space for Ultra-Thin-Body GeOI/SOI Negative Capacitance FETs
|
Lee, Ho-Pei; Yu, Chien-Lin; You, Wei-Xiang; Su, Pin |
| 國立交通大學 |
2018-08-21T05:56:52Z |
Exploration and Evaluation of TCAM with Hybrid Tunneling FET and FinFET Devices for Ultra-Low-Voltage Applications
|
Tu, Meng-Hsuan; Chen, Yin-Nien; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2018-08-21T05:56:52Z |
Design Space Exploration Considering Back-Gate Biasing Effects for Negative-Capacitance Transition-Metal-Dichalcogenide (TMD) Field-Effect Transistors
|
You, Wei-Xiang; Su, Pin |
| 國立交通大學 |
2018-08-21T05:54:20Z |
Design Space Exploration Considering Back-Gate Biasing Effects for 2D Negative-Capacitance Field-Effect Transistors
|
You, Wei-Xiang; Su, Pin |
| 國立交通大學 |
2018-08-21T05:53:58Z |
Performance and Stability Benchmarking of Monolithic 3-D Logic Circuits and SRAM Cells With Monolayer and Few-Layer Transition Metal Dichalcogenide MOSFETs
|
Yu, Chang-Hung; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2018-08-21T05:53:27Z |
Short-Channel Effects in 2D Negative-Capacitance Field-Effect Transistors
|
You, Wei-Xiang; Tsai, Chih-Peng; Su, Pin |
| 國立交通大學 |
2018-08-21T05:52:50Z |
Suppressed Fin-LER Induced Variability in Negative Capacitance FinFETs
|
Lee, Ho-Pei; Su, Pin |
| 國立成功大學 |
2018-03 |
Validating the creative self-efficacy student scale with a Taiwanese sample: An item response theory-based investigation
|
Hung;Su-Pin |
| 國立交通大學 |
2018-01-24T07:42:42Z |
鰭狀式場效電晶體之特性分析及堆疊式環狀閘極場效電晶體於邏輯電路應用中最佳堆疊層數之探討
|
黃威程; 蘇彬; Huang, Wei-Cheng; Su, pin |
| 國立交通大學 |
2018-01-24T07:42:15Z |
二維過渡金屬硫屬化合物及堆疊式奈米線元件之靜態隨機存取記憶體分析與研究
|
鄭峻騰; 蘇彬; Zheng, Chun-Teng; Su Pin |
| 國立交通大學 |
2018-01-24T07:40:33Z |
鍺通道超薄絕緣層負電容金氧半場效電晶體之設計空間及負電容鰭狀電晶體之鰭邊緣粗糙引發之變異度分析
|
李禾培; 蘇彬; Lee, Ho-Pei; Su, Pin |
| 國立交通大學 |
2018-01-24T07:38:55Z |
混合穿隧式場效電晶體與鰭式場效電晶體的三態內容可定址記憶體電路超低壓應用之研究與分析
|
杜孟軒; 莊景德; 蘇彬; Tu, Meng-Hsuan; Chuang,Ching-Te; Su,Pin |
| 國立交通大學 |
2018-01-24T07:38:53Z |
量子電容效應於超薄單閘極與雙閘極及閘極全包覆式三五族金氧半場效電晶體 閘極反轉層電容値之比較與模型建立
|
沈仕倫; 蘇彬; Shen, Shih-Lun; Su, Pin |
| 國立交通大學 |
2018-01-24T07:38:53Z |
超薄絕緣三五族金氧半場效電晶體與負電容場效電晶體之量子次臨界模型建立
|
余建霖; 蘇彬; Yu, Chien-Lin; Su, Pin |
| 國立交通大學 |
2018-01-24T07:38:51Z |
超薄絕緣層異質三五族與鍺通道金氧半場效電晶體及單層與多層二維過渡金屬硫屬化合物之邏輯電路及靜態隨機存取記憶體之研究與分析
|
余昌鴻; 蘇彬; Yu, Chang-Hung; Su, Pin |
| 國立交通大學 |
2018-01-24T07:38:13Z |
全包覆式閘極三五族穿隧式電晶體的直徑最佳化及短通道效應之理論探討
|
王佑瑋; 蘇彬; Wang, Yu-Wei; Su, Pin |
