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Taiwan Academic Institutional Repository >
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"su pin"
Showing items 51-75 of 198 (8 Page(s) Totally)
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| 國立交通大學 |
2018-01-24T07:36:57Z |
高遷移率通道三閘極電晶體 之靜電完整性的理論研究
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吳杼樺; 蘇彬; Wu, Shu-Hua; Su, Pin |
| 國立交通大學 |
2017-04-21T06:56:35Z |
A Compact Subthreshold Model for Short-Channel Monolayer Transition Metal Dichalcogenide Field-Effect Transistors
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You, Wei-Xiang; Su, Pin |
| 國立交通大學 |
2017-04-21T06:56:15Z |
Impact of Random Variations on Cell Stability and Write-Ability of Low-Voltage SRAMs Using Monolayer and Bilayer Transition Metal Dichalcogenide (TMD) MOSFETs
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Yu, Chang-Hung; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2017-04-21T06:55:34Z |
Investigation and Simulation of Work-Function Variation for III-V Broken-Gap Heterojunction Tunnel FET
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Hsu, Chih-Wei; Fan, Ming-Long; Hu, Vita Pi-Ho; Su, Pin |
| 國立交通大學 |
2017-04-21T06:50:14Z |
Anomalous Electrostatics and Intrinsic Variability in GeOI p-MOSFET
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Yu, Chang-Hung; Su, Pin |
| 國立交通大學 |
2017-04-21T06:50:10Z |
Evaluation of Energy-Efficient Latch Circuits with Hybrid Tunneling FET and FinFET Devices for Ultra-Low-Voltage Applications
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Wu, Tse-Ching; Chen, Chien-Ju; Chen, Yin-Nien; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2017-04-21T06:50:05Z |
Investigation of BTI Reliability for Monolithic 3D 6T SRAM with Ultra-thin-body GeOI MOSFETs
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Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2017-04-21T06:49:57Z |
Impacts of Work Function Variation and Line-Edge Roughness on TFET and FinFET Devices and Logic Circuits
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Chen, Chien-Ju; Chen, Yin-Nien; Fan, Ming-Long; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2017-04-21T06:49:47Z |
UTB GeOI 6T SRAM Cell and Sense Amplifier considering BTI Reliability
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Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2017-04-21T06:49:44Z |
Built-in Effective Body-Bias Effect in UTBB Hetero-Channel MOSFETs and Its Suppression
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Yu, Chang-Hung; Su, Pin |
| 國立交通大學 |
2017-04-21T06:49:30Z |
Investigation and Benchmark of Intrinsic Drain-Induced-Barrier-Lowering (DIBL) for Ultra-Thin-Body III-V-on-Insulator n-MOSFETs
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Yu, Chang-Hung; Su, Pin |
| 國立交通大學 |
2017-04-21T06:49:25Z |
Stability Optimization of Monolithic 3-D MoS2-n/WSe2-p SRAM Cells for Superthreshold and Near-/Sub-threshold Applications
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Yu, Chang-Hung; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2017-04-21T06:49:25Z |
Performance Benchmarking of Monolayer and Bilayer Two-Dimensional Transition Metal Dichalcogenide (TMD) Based Logic Circuits
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Yu, Chang-Hung; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2017-04-21T06:49:09Z |
Corner Spacer Design for Performance Optimization of Multi-Gate InGaAs-OI FinFET with Gate-to-Source/Drain Underlap
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Hu, Vita Pi-Ho; Lo, Chang-Ting; Sachid, Angada B.; Su, Pin; Hu, Chenming |
| 國立交通大學 |
2017-04-21T06:49:08Z |
Accurate modeling and characterization of mobility in tensile and compressive stress for state-of-the-art manufacturing NMOSFETs
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Wang, J. -S.; Chen, William P. N.; Shih, C. -H.; Lien, C.; Su, Pin; Sheu, Y. M.; Chao, Donald Y. -S.; Goto, K. |
| 國立交通大學 |
2017-04-21T06:49:05Z |
Evaluation of TFET and FinFET Devices and 32-Bit CLA Circuits Considering Work Function Variation and Line-Edge Roughness
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Chen, Chien-Ju; Chen, Yin-Nien; Fan, Ming-Long; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2017-04-21T06:49:02Z |
Impacts of NBTI and PBTI on Ultra-Thin-Body GeOI 6T SRAM Cells
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Hu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2017-04-21T06:48:32Z |
Evaluation of 32-Bit Carry-Look-Ahead Adder Circuit with Hybrid Tunneling FET and FinFET Devices
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Wu, Tse-Ching; Chen, Chien-Ju; Chen, Yin-Nien; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2017-04-21T06:48:17Z |
Simulation of Grain-Boundary Induced V-th Variability in Stackable NAND Flash Using a Voronoi Approach
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Yang, Ching-Wei; Chao, Shao-Heng; Su, Pin |
| 國立交通大學 |
2016-03-28T08:17:18Z |
二維材料金氧半元件於邏輯電路與記憶體應用之適用性評估(I)
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蘇彬; Su Pin |
| 國立交通大學 |
2016-03-28T00:04:24Z |
Evaluation of Monolayer and Bilayer 2-D Transition Metal Dichalcogenide Devices for SRAM Applications
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Yu, Chang-Hung; Fan, Ming-Long; Yu, Kuan-Chin; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2016-03-28T00:04:17Z |
Impact of Quantum Capacitance on Intrinsic Inversion Capacitance Characteristics and Inversion-Charge Loss for Multigate III-V-on-Insulator nMOSFETs
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Shen, Hsin-Hung; Shen, Shih-Lun; Yu, Chang-Hung; Su, Pin |
| 國立交通大學 |
2015-12-02T03:00:54Z |
Stability/Performance Assessment of Monolithic 3D 6T/ST SRAM Cells Considering Transistor-Level Interlayer Coupling
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Fan, Ming-Long; Hu, Vita Pi-Ho; Chen, Yin-Nien; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2015-11-26T01:07:47Z |
超薄絕緣鍺金氧半場效電晶體在量子侷限下的短通道效應模型與分析
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謝欣原; Hsieh, Hsin-Yuan; 蘇彬; Su, Pin |
| 國立交通大學 |
2015-11-26T01:02:59Z |
Spacer之設計對多重閘極絕緣砷化銦鎵金氧半鰭狀式場效電晶體的靜電完整性及效能的影響
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羅章庭; Lo, Chang-Ting; 蘇彬; Su, Pin |
Showing items 51-75 of 198 (8 Page(s) Totally)
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