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Showing items 31-40 of 58  (6 Page(s) Totally)
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Institution Date Title Author
臺大學術典藏 2018-09-10T08:47:23Z Spilt-based Digital Background Calibration of Multistage Nonlinear Errors in Pipelined ADCS P Zhang; T-C Lee; TAI-CHENG LEE
臺大學術典藏 2018-09-10T08:47:23Z Method for achieving high-speed analog-to-digital conversion without degrading accuracy, and associated apparatus L-H Hung; T-C Lee; TAI-CHENG LEE
臺大學術典藏 2018-09-10T08:47:23Z Digital-to-analog converter (DAC) and an associated method T-C Lee; C-H Lin; TAI-CHENG LEE
臺大學術典藏 2018-09-10T08:19:09Z Nonlinear R-2R Transistor-Only DAC T-C Lee;C-H Lin; T-C Lee; C-H Lin; TAI-CHENG LEE
臺大學術典藏 2018-09-10T08:19:09Z An Offset Phase-Locked Loop Spread Spectrum Clock Generator for SATA III C-Y Lin;C-Y Chiang;T-C Lee; C-Y Lin; C-Y Chiang; T-C Lee; TAI-CHENG LEE
臺大學術典藏 2018-09-10T08:19:09Z A 300- to 800-MHz De-Skew Clock Generator for Arbitrary Delay Y-C Hung;K Fong;T-C Lee; Y-C Hung; K Fong; T-C Lee; TAI-CHENG LEE
臺大學術典藏 2018-09-10T08:19:08Z A 320-MHz CMOS Continuous-Time ΔΣ Modulator With 5-MHz Signal Bandwidth and 8.3-bit ENOB K-T Chen;T-C Lee; K-T Chen; T-C Lee; TAI-CHENG LEE
臺大學術典藏 2018-09-10T07:09:31Z A Fully Integrated 36MHz to 230MHz Multiplying DLL with Adaptive Current Tuning K-J Hsiao; T-C Lee; TAI-CHENG LEE
臺大學術典藏 2018-09-10T06:37:54Z A Fully Integrated 36MHz to 230MHz Multiplying DLL with Adaptive Current Tuning K-J Hsiao; T-C Lee; TAI-CHENG LEE
臺大學術典藏 2018-09-10T06:37:53Z A Delay-Line-Based GFSK Demodulator for Low-IF Receivers H-S Kao; M-J Yang; T-C Lee; TAI-CHENG LEE

Showing items 31-40 of 58  (6 Page(s) Totally)
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