臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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	2019臺灣學術機構典藏研討會
	機構典藏系統RC7版本已發佈

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	臺大學術典藏NTU Scholars

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Institution	Date	Title	Author
元智大學	2013-06	Fire Computer-Simulated Fire Scene Verification of Entertainment Establishments	Cherng-Shing Lin; Te-Chi Chen; Tai-Yi Lee
元智大學	2013-05	Fire Computer-Simulated Fire Scene Verification of Entertainment Establishments	Cherng-Shing Lin; Te-Chi Chen; Tai-Yi Lee
元智大學	2012	台中市ALA PUB火災火場驗證與逃生避難模擬研究	李泰儀; Tai-Yi Lee
國立中山大學	2009-07	Improving Reliability and Diminishing Parasitic Capacitance Effects in a Vertical Transistor with Embedded Gate	Jyi-Tsong Lin;Chih-Hao Kuo;Tai-Yi Lee;Yi-Chuen Eng;Tzu-Feng Chang;Po-Hsieh Lin;Hsuan-Hsu Chen
國立中山大學	2009-06	The impact of Junction Depth on Vertical Sidewall MOSFETs with Embedded Gate	Chih-Hao Kuo;Jyi-Tsong Lin;Tai-Yi Lee;Yi-Chuen Eng;Tzu-Feng Chang;Po-Hsieh Lin;Hsuan-Hsu Chen;Chih-Hung Sun;Hsien-Nan Chiu
國立中山大學	2009-05	An Improved Vertical Embedded Sidewall-Gate MOSFET for Reducing Parasitic Capacitance and Suppressing Kink Effects	Chih-Hao Kuo;Jyi-Tsong Lin;Tai-Yi Lee;Yi-Chuen Eng;Tzu-Feng Chang
國立中山大學	2009-04	A Vertical Transistor with Embedded Gate for Reducing Parasitic Overlap Capacitance	Chih-Hao Kuo;Jyi-Tsong Lin;Tai-Yi Lee;Yi-Chuen Eng;Tzu-Feng Chang
國立中山大學	2008-10	Novel Vertical Sidewall MOSFETs with Embedded Gate	Tai-Yi Lee;Jyi-Tsong Lin;Kao-Cheng Lin
國立中山大學	2008-05	A 2-D simulation study and characterization of a novel vertical SOI MOSFET with a smart source body tie	Jyi-Tsong Lin;Tai-Yi Lee;Kao-Cheng Lin
國立中山大學	2008-05	The Novel Embedded Vertical Sidewall MOSFETs	Jyi-Tsong Lin;Tai-Yi Lee;Kao-Cheng Lin
國立中山大學	2008-05	A Novel Vertical Sidewall MOSFET Using Smart Source/Body Contact without Floating-Body Effect	Tai-Yi Lee;Jyi-Tsong Lin;Yi-Chuen Eng;Kao-Cheng Lin
國立中山大學	2008-05	A Novel Vertical Sidewall MOSFETs Using Smart Source/Body Contact without Floating-Body Effect	Tai-Yi Lee;Jyi-Tsong Lin;Po-Hsieh Lin;Yi-Chuen Eng
國立中山大學	2007-05	Investigation of the Novel attribution in A new Vertical MOSFET with Upper and Internal L-shape Buried Oxide	Jyi-Tsong Lin;Tai-Yi Lee;Kao-Cheng Lin;Yu-Sheng Chen
國立中山大學	2007-01	Analysis of Si-body Thickness Variation for a new 40 nm Gate Length bFDSOI	Jyi-Tsong Lin;Yi-Chuen Eng;Tai-Yi Lee;Kao-Cheng Lin
國立中山大學	2006-11	Investigation Of The Novel Attribution In A New Vertical MOSFET With Upper And Internal L-Shape Buried Oxide	Jyi-Tsong Lin;Yu-Sheng Chen;Tai-Yi Lee;Kao-Cheng Lin
國立中山大學	2006-10	An Investigation of the effects of Si thickness-induced variation of the electrical characteristics in FDSOI with block oxide	Yi-Chuen Eng;Jyi-Tsong Lin;Kuo-Dong Huang;Tai-Yi Lee;Kao-Cheng Lin
國立中山大學	2006-10	A Nanoscale bSPIFET to Overcome CMOS Scaling	Jyi-Tsong Lin;Yi-Chuen Eng;Tai-Yi Lee;Kao-Cheng Lin
國立中山大學	2006-07	Ultra-Short-Channel Characteristics of Planar MOSFETs with Block Oxide	Jyi-Tsong Lin;Yi-Chuen Eng;Kuo-Dong Huang;Tai-Yi Lee;Kao-Cheng Lin
國立中山大學	2006-07	HIGH PERFORMANCE THIN-FILM TRANSISTOR WITH L-SHAPED BLOCK OXIDE	Jyi-Tsong Lin;Yi-Chuen Eng;Tai-Yi Lee;Kao-Cheng Lin;Kuo-Dong Huang
國立中山大學	2006-05	Investigation of a Pseudo Vertical SOI MOSFET With L-Shaped Block Layer	Jyi-Tsong Lin;Kao-Cheng Lin;Tai-Yi Lee;Yi-Chuen Eng
國立中山大學	2006-05	A Novel Vertical MOSFET with Smart Source/ Body Contact	Tai-Yi Lee;Jyi-Tsong Lin;Yi-Chuen Eng;Kao-Cheng Lin
國立中山大學	2006-05	A Novel Device Architecture: Silicon on Partial Insulator with Block Oxide	Jyi-Tsong Lin;Yi-Chuen Eng;Tai-Yi Lee;Kao-Cheng Lin
國立中山大學	2006-05	Elimination of Floating-body Effect and Thermal Instability in a Nano Quasi-SOI MOSFET with π-shaped Semiconductor Layer	Jyi-Tsong Lin;Yi-Chuen Eng;Tai-Yi Lee;Kao-Cheng Lin
國立中山大學	2006-05	A NOVEL FDSOI MOSFET WITH BLOCK OXIDE ENCLOSED BODY	Jyi-Tsong Lin;Yi-Chuen Eng;Kuo-Dong Huang;Tai-Yi Lee;Kao-Cheng Lin
國立中山大學	2006-05	Investigation of the Novel Attributes of a Vertical MOSFET Device with Internal Block Layer: a 2D Simulation Study	Jyi-Tsong Lin;Kao-Cheng Lin;Tai-Yi Lee;Yi-Chuen Eng

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