臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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Showing items 1-10 of 27 (3 Page(s) Totally)
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Institution	Date	Title	Author
元智大學	2013-06	Fire Computer-Simulated Fire Scene Verification of Entertainment Establishments	Cherng-Shing Lin; Te-Chi Chen; Tai-Yi Lee
元智大學	2013-05	Fire Computer-Simulated Fire Scene Verification of Entertainment Establishments	Cherng-Shing Lin; Te-Chi Chen; Tai-Yi Lee
元智大學	2012	台中市ALA PUB火災火場驗證與逃生避難模擬研究	李泰儀; Tai-Yi Lee
國立中山大學	2009-07	Improving Reliability and Diminishing Parasitic Capacitance Effects in a Vertical Transistor with Embedded Gate	Jyi-Tsong Lin;Chih-Hao Kuo;Tai-Yi Lee;Yi-Chuen Eng;Tzu-Feng Chang;Po-Hsieh Lin;Hsuan-Hsu Chen
國立中山大學	2009-06	The impact of Junction Depth on Vertical Sidewall MOSFETs with Embedded Gate	Chih-Hao Kuo;Jyi-Tsong Lin;Tai-Yi Lee;Yi-Chuen Eng;Tzu-Feng Chang;Po-Hsieh Lin;Hsuan-Hsu Chen;Chih-Hung Sun;Hsien-Nan Chiu
國立中山大學	2009-05	An Improved Vertical Embedded Sidewall-Gate MOSFET for Reducing Parasitic Capacitance and Suppressing Kink Effects	Chih-Hao Kuo;Jyi-Tsong Lin;Tai-Yi Lee;Yi-Chuen Eng;Tzu-Feng Chang
國立中山大學	2009-04	A Vertical Transistor with Embedded Gate for Reducing Parasitic Overlap Capacitance	Chih-Hao Kuo;Jyi-Tsong Lin;Tai-Yi Lee;Yi-Chuen Eng;Tzu-Feng Chang
國立中山大學	2008-10	Novel Vertical Sidewall MOSFETs with Embedded Gate	Tai-Yi Lee;Jyi-Tsong Lin;Kao-Cheng Lin
國立中山大學	2008-05	A 2-D simulation study and characterization of a novel vertical SOI MOSFET with a smart source body tie	Jyi-Tsong Lin;Tai-Yi Lee;Kao-Cheng Lin
國立中山大學	2008-05	The Novel Embedded Vertical Sidewall MOSFETs	Jyi-Tsong Lin;Tai-Yi Lee;Kao-Cheng Lin

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