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Showing items 1-2 of 2 (1 Page(s) Totally) 1 View [10|25|50] records per page
國立交通大學 |
2018-08-21T05:53:00Z |
ULV-Turbo Cache for an Instantaneous Performance Boost on Asymmetric Architectures
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Wang, Po-Hao; Chien, Yung-Chen; Tsai, Shang-Jen; Lin, Xuan-Yu; Tanjung, Rizal; Lin, Yi-Sian; Syu, Shu-Wei; Lin, Tay-Jyi; Wang, Jinn-Shyan; Chen, Tien-Fu |
國立交通大學 |
2017-04-21T06:56:22Z |
Cross-matching caches: Dynamic timing calibration and bit-level timing-failure mask caches to reduce timing discrepancies with low voltage processors
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Wang, Po-Hao; Tsai, Shang-Jen; Tanjung, Rizal; Lin, Tay-Jyi; Wang, Jinn-Shyan; Chen, Tien-Fu |
Showing items 1-2 of 2 (1 Page(s) Totally) 1 View [10|25|50] records per page
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