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Showing items 1-6 of 6 (1 Page(s) Totally)
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| 國立交通大學 |
2014-12-08T15:41:09Z |
Inductance modeling for on-chip interconnects
|
Tu, SW; Shen, WZ; Chang, YW; Chen, TC; Jou, JY |
| 國立交通大學 |
2014-12-08T15:26:37Z |
Inductance modeling for on-chip interconnects
|
Tu, SW; Shen, WZ; Chang, YW; Chen, TC |
| 國立交通大學 |
2014-12-08T15:25:57Z |
RLC effects on worst-case switching pattern for on-chip buses
|
Tu, SW; Jou, JY; Chang, YW |
| 國立交通大學 |
2014-12-08T15:25:40Z |
Layout techniques for on-chip interconnect inductance reduction
|
Tu, SW; Jou, JY; Chang, YW |
| 國立交通大學 |
2014-12-08T15:25:38Z |
On-chip bus encoding for LC cross-talk reduction
|
Huang, JS; Tu, SW; Jou, JY |
| 國立交通大學 |
2014-12-08T15:25:24Z |
RLC coupling-aware simulation for on-chip buses and their encoding for delay reduction
|
Tu, SW; Jou, JY; Chang, YW |
Showing items 1-6 of 6 (1 Page(s) Totally)
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