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Showing items 1-17 of 17  (1 Page(s) Totally)
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Institution Date Title Author
國立中山大學 2009-11 A Non-Classical Self-Aligned _-Shaped Source/Drain Ultrathin SOI Transistor for Future Planar MOSFET Technology Jyi-Tsong Lin;Yi-Chuen Eng;Po-Hsieh Lin;Tzu-Feng Chang;Chih-Hung Sun;Chih-Hao Kuo
國立中山大學 2009-07 Characteristics of a Local Oxidation of silicon multi-tie body polysilicon thin-film transistor Hsien-Nan Chiu;Jyi-Tsong Lin;Yi-Chuen Eng;Po-Hiesh Lin;Tzu-Feng Chang;Chih-Hung Sun;Hsuan-Hsu Chen;Chih-Hao Kuo
國立中山大學 2009-07 A simulation study of source/drain-tie effects on characteristics of self-aligned π-shaped source/drain ultrathin SOI FETs Yi-Chuen Eng;Jyi-Tsong Lin;Tzu-Feng Chang
國立中山大學 2009-07 Advanced Block Oxide MOSFETs for 25 nm Technology Node Chih-Hung Sun;Jyi-Tsong Lin;Yi-Chuen Eng;Tzu-Feng Chang;Po-Hiesh Lin;Hsuan-Hsu Chen;Chih-Hao Kuo;Hsien-Nan Chiu
國立中山大學 2009-07 Self-Aligned SOI MOSFETs with Ω-Shaped Conductive Layer and Source/Drain-Tie Jyi-Tsong Lin;Tzu-Feng Chang;Yi-Chuen Eng;Hsuan-Hsu Chen;Chih-Hao Kuo;Chih-Hung Sun;Po-Hiesh Lin;Hsien-Nan Chiu
國立中山大學 2009-07 Improving Reliability and Diminishing Parasitic Capacitance Effects in a Vertical Transistor with Embedded Gate Jyi-Tsong Lin;Chih-Hao Kuo;Tai-Yi Lee;Yi-Chuen Eng;Tzu-Feng Chang;Po-Hsieh Lin;Hsuan-Hsu Chen
國立中山大學 2009-06 The impact of Junction Depth on Vertical Sidewall MOSFETs with Embedded Gate Chih-Hao Kuo;Jyi-Tsong Lin;Tai-Yi Lee;Yi-Chuen Eng;Tzu-Feng Chang;Po-Hsieh Lin;Hsuan-Hsu Chen;Chih-Hung Sun;Hsien-Nan Chiu
國立中山大學 2009-05 Self-Aligned Silicon-On-Insulator MOSFETs with Ω-Shaped Conductive Layer Tzu-Feng Chang;Jyi-Tsong Lin;Yi-Chuen Eng;Chih-Hung Sun;Po-Hiesh Lin;Hsien-Nan Chiu;Hsuan-Hsu Chen;Chih-Hao Kuo
國立中山大學 2009-05 A Novel Poly-silicon Thin-Film Transistor with Multi-Trenched Body Formed by Using Isotropic-etching for Suppressing Off-State Leakage Hsien-Nan Chiu;Jyi-Tsong Lin;Yi-Chuen Eng;Po-Hiesh Lin;Tzu-Feng Chang;Chih-Hung Sun;Chih-Hao Kuo;Hsuan-Hsu Chen
國立中山大學 2009-05 Self-Aligned Block-Oxide Quasi-SOI MOSFETs with S/D-Tie Chih-Hung Sun; Jyi-Tsong Lin; Yi-Chuen Eng; Tzu-Feng Chang; Po-Hiesh Lin; Hsuan-Hsu Chen; Chih-Hao Kuo; Hsien-Nan Chiu
國立中山大學 2009-05 An Improved Vertical Embedded Sidewall-Gate MOSFET for Reducing Parasitic Capacitance and Suppressing Kink Effects Chih-Hao Kuo;Jyi-Tsong Lin;Tai-Yi Lee;Yi-Chuen Eng;Tzu-Feng Chang
國立中山大學 2009-05 Future of Planar Self-Aligned Block Oxide Based MOSFET Technology Jyi-Tsong Lin;Yi-Chuen Eng;Chih-Hao Kuo;Tzu-Feng Chang;Chih-Hung Sun;Po-Hsieh Lin;Hsien-Nan Chiu;Hsuan-Hsu Chen
國立中山大學 2009-05 A Novel Poly-Si Thin-Film Transistor with Multi-Trenched Body by Using Isotropic-etching for Suppressing Off-State Leakage Hsien-Nan Chiu;Jyi-Tsong Lin;Yi-Chuen Eng;Po-Hiesh Lin;Tzu-Feng Chang;Chih-Hung Sun;Chih-Hao Kuo;Hsuan-Hsu Chen
國立中山大學 2009-04 A Vertical Transistor with Embedded Gate for Reducing Parasitic Overlap Capacitance Chih-Hao Kuo;Jyi-Tsong Lin;Tai-Yi Lee;Yi-Chuen Eng;Tzu-Feng Chang
國立中山大學 2009-04 A Novel Polysilicon Thin-Film Transistor with Multi-Trenched Body by Using Isotropic-etching for Suppressing Off-State Leakage Hsien-Nan Chiu;Jyi-Tsong Lin;Yi-Chuen Eng;Po-Hiesh Lin;Tzu-Feng Chang
國立中山大學 2009-04 Study of bMOS and bMPI for 25 nm technology node Chih-Hung Sun; Jyi-Tsong Lin; Yi-Chuen Eng; Tzu-Feng Chang; Po-Hiesh Lin; Hsuan-Hsu Chen; Chih-Hao Kuo; Hsien-Nan Chiu
國立中山大學 2009-04 Self-Aligned Silicon-On-Insulator Transistors with Ω-Shaped Conductive Layer and Source/Drain-Tie: A Simulation Study Tzu-Feng Chang;Jyi-Tsong Lin;Yi-Chuen Eng;Chih-Hao Kuo;Chih-Hung Sun;Po-Hiesh Lin;Hsien-Nan Chiu;Hsuan-Hsu Chen

Showing items 1-17 of 17  (1 Page(s) Totally)
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